XR16L570_07 Datasheet, PDF (31/47 Pages) Exar Corporation – SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE

XR16L570
REV. 1.0.1
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
MSR[3]: Delta CD# Input Flag
Since the 24-QFN package of the L570 does not have the CD# modem input, this bit has functionality only in
internal loopback mode when the CD bit (MSR[7]) can be controlled via the OP2# bit (MCR[3]).
• Logic 0 = No change on CD# input (default).
• Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem
status interrupt will be generated if MSR interrupt is enabled (IER bit-3).
MSR[4]: CTS Input Status
CTS# pin may function as automatic hardware flow control signal input if it is enabled and selected by Auto
CTS (EFR bit-7). Auto CTS flow control allows starting and stopping of local data transmissions based on the
modem CTS# signal. A logic 1 on the CTS# pin will stop UART transmitter as soon as the current character
has finished transmission, and a logic 0 will resume data transmission. Normally MSR bit-4 bit is the
complement of the CTS# input. However in the loopback mode, this bit is equivalent to the RTS# bit in the
MCR register. The CTS# input may be used as a general purpose input when the modem interface is not used.
MSR[5]: DSR Input Status
Normally MSR bit-5 is the complement of the DSR# input in the 32-QFN package. In internal loopback mode,
this bit is equivalent to the DTR# bit (MCR[0]). The 24-QFN package of the L570 does not have the DSR#
modem input.
MSR[6]: RI Input Status
Normally MSR bit-6 is the complement of the RI# input in the 32-QFN package. In internal loopback mode, this
bit is equivalent to the OP1# bit (MCR[2]). The 24-QFN package of the L570 does not have the RI# modem
input.
MSR[7]: CD Input Status
Normally MSR bit-5 is the complement of the CD# input in the 32-QFN package. In internal loopback mode,
this bit is equivalent to the OP2# bit (MCR[3]). The 24-QFN package of the L570 does not have the CD#
modem input.
4.11 Scratchpad Register (SPR) - Read/Write
This is a 8-bit general purpose register for the user to store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.
4.12 Baud Rate Generator Registers (DLL and DLM) - Read/Write
The concatenation of the contents of DLM and DLL gives the 16-bit divisor value which is used to calculate the
baud rate:
• Baud Rate = (Clock Frequency / 16) / Divisor
See MCR bit-7 and the baud rate table also.
4.13 Device Identification Register (DVID) - Read Only
This register contains the device ID (0x01 for XR16L570). Prior to reading this register, DLL and DLM should
be set to 0x00.
4.14 Device Revision Register (DREV) - Read Only
This register contains the device revision information. For example, 0x01 means revision A. Prior to reading
this register, DLL and DLM should be set to 0x00.
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