XR16L570_07 Datasheet, PDF (18/47 Pages) Exar Corporation – SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE

XR16L570
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
REV. 1.0.1
2.19 Internal Loopback
The L570 UART provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally
including automatic hardware and software flow control. Figure 13 shows how the modem port signals are re-
configured. The general purpose outputs OP1#, OP2#, the modem output DTR# and the modem inputs DSR#,
RI# and CD# are not available in the 24-QFN package of the L570. However, in internal loopback mode, the
DTR#, OP1# and OP2# bits in the MCR register, control the DSR#, RI# and CD# bits in the MSR register
respectively. Transmit data from the transmit shift register output is internally routed to the receive shift register
input allowing the system to receive the same data that it was sending. The TX pin is held HIGH while RTS# is
de-asserted, and CTS# input is ignored. Caution: the RX input pins must be held HIGH during loopback test
else upon exiting the loopback test the UART may detect and report a false “break” signal.
FIGURE 13. INTERNAL LOOP BACK
Transmit Shift Register
(THR/FIFO)
VCC
MCR bit-4=1
Receive Shift Register
(RHR/FIFO)
VCC
RTS#
CTS#
VCC
DTR#
DSR#
RI#
OP1#
CD#
OP2#
TX
RX
RTS#
CTS#
DTR#
DSR#
RI#
CD#
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