English
Language : 

XRT94L43_06 Datasheet, PDF (305/328 Pages) Exar Corporation – SONET/SDH OC-12 TO 12XDS3/E3 MAPPER
◁
XRT94L43
SONET/SDH OC-12 TO 12XDS3/E3 MAPPER
FIGURE 12. SYNCHRONOUS MODE 4 - IDT3051/52 INTERFACE TIMING (READ CYCLE)
pCLK
pCS_L
pALE
pA[7:0]
pD[7:0]
pRdy_L
pRD_L
pWR_L
Address
t5
t7
Data
t8
t9
t10
pDBEN_L
t11
REV. 1.0.2
NOTE: The values for t0 through t11 can be found in Table 4.
TABLE 4: TIMING INFORMATION FOR THE MICROPROCESSOR INTERFACE, WHEN CONFIGURED TO OPERATE IN THE
IDT3051/52 MODE
TIMING
DESCRIPTION
MIN.
TYP.
t0
pCS_L low to Clock high
6
-
t1
pALE high to Clock high
1
-
t2
Clock high to pALE low
6
-
t3
Data setup time (WRITE cycle)
-
-
t4
Data hold time (WRITE cycle)
-
-
t5
Clock high to pRDY_L low
-
-
t6
Clock high to pWR_L high
6
-
t7
Clock high to Data valid (READ cycle)
-
-
t8
Clock high to pRDY_L high
-
-
t9
pRDY_L high to Data invalid
0
-
t10
Clock high to pRD_L high
11
-
t11
Clock high to pDBEN_L high
10
-
NOTE: Test Conditions: TA = 25°C, VCC = 3.3V±5% and 2.5V±5%, unless otherwise specified.
2.0 STS-12/STM-4 TELECOM BUS INTERFACE TIMING INFORMATION
MAX.
-
-
-
N/N
N/N
11
-
N/N
11
-
-
-
299
 ▷