XRK4993 Datasheet, PDF (3/13 Pages) Exar Corporation – 3.3V PROGRAMMABLE SKEW CLOCK BUFFER

REV. 1.0.0
PIN DESCRIPTIONS
XRK4993
3.3V PROGRAMMABLE SKEW CLOCK BUFFER
PIN NAME
CLKIN
FB_IN
PLL_BYPASS
OE
PE
SELA0
SELA1
SELB0
SELB1
SELC0
SELC1
FSEL
QA0
QA1
QB0
QB1
QC0
QC1
QD0
QD1
V_CCN
V_CCQ
GND
PIN #
1
14
27
24
6
22
23
25
26
4
5
3
20
19
16
15
12
11
9
8
7
13
21
2
TYPE
DESCRIPTION
Input Reference Clock Input
Input Feedback Input
Three- When MID or HIGH, disables PLL (see Special Functions). CLKIN goes to all out-
level puts. Skew Selections (see Control Summary Table) remain in effect. Set LOW
Input for normal operations.
Input
Synchronous Output Enable. When HIGH, it stops clock outputs (except QC[1:0]).
QC[1:0] may be used as the feedback signal to maintain phase lock. Set OE
LOW for normal operation.
Input Selectable positive or negative edge control. When LOW/HIGH the outputs are
synchronized with the falling/rising edge of the reference clock.
Three- 3-level inputs for selecting 1 of 9 skew taps or frequency functions.
level
Input
Three-
level
Input
Three-
level
Input
Three- Selects appropriate oscillator circuit based on anticipated frequency range. (See
level PLL Programmable Skew Range.)
Input
Output Three output banks of two outputs with programmable skew (QA[1:0], QB[1:0],
QC[1:0]). QD[1:0] outputs have fixed zero skew outputs.
Output
Output
Output
PWR Power supply for output buffers.
PWR Power supply for phase locked loop and other internal circuitry.
10 PWR Ground.
17
18
28
3