XR16L2450_05 Datasheet, PDF (3/30 Pages) Exar Corporation – 2.25V TO 5.5V DUART

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REV. 1.1.1
XR16L2450
2.25V TO 5.5V DUART
PACKAGE PIN DESCRIPTIONS
PIN DESCRIPTIONS
NAME
44-PLCC
PIN #
48-TQFP
PIN #
TYPE
DESCRIPTION
DATA BUS INTERFACE
A2
29
26
I Address data lines [2:0]. These 3 address lines select one of the inter-
A1
30
27
nal registers in UART channel A/B during a data bus transaction.
A0
31
28
D7
9
3
IO Data bus lines [7:0] (bidirectional).
D6
8
2
D5
7
1
D4
6
48
D3
5
47
D2
4
46
D1
3
45
D0
2
44
IOR#
24
19
I Input/Output Read Strobe (active low). The falling edge instigates an
internal read cycle and retrieves the data byte from an internal register
pointed to by the address lines [A2:A0]. The data byte is placed on the
data bus to allow the host processor to read it on the rising edge.
IOW#
20
15
I Input/Output Write Strobe (active low). The falling edge instigates an
internal write cycle and the rising edge transfers the data byte on the
data bus to an internal register pointed by the address lines.
CSA#
16
10
I UART channel A select (active low) to enable UART channel A in the
device for data bus operation.
CSB#
17
11
I UART channel B select (active low) to enable UART channel B in the
device for data bus operation.
INTA
33
30
O UART channel A Interrupt output. The output state is defined by the
user and through the software setting of MCR[3]. INTA is set to the
active mode and OP2A# output to a logic 0 when MCR[3] is set to a
logic 1. INTA is set to the three state mode and OP2A# to a logic 1
when MCR[3] is set to a logic 0 (default).
INTB
32
29
O UART channel B Interrupt output. The output state is defined by the
user and through the software setting of MCR[3]. INTB is set to the
active mode and OP2B# output to a logic 0 when MCR[3] is set to a
logic 1. INTB is set to the three state mode and OP2B# to a logic 1
when MCR[3] is set to a logic 0 (default).
MODEM OR SERIAL I/O INTERFACE
TXA
13
7
O UART channel A Transmit Data. If it is not used, leave it unconnected.
RXA
11
5
I UART channel A Receive Data. Normal receive data input must idle at
logic 1 condition. If it is not used, tie it to VCC or pull it high via a 100k
ohm resistor.
RTSA#
36
33
O UART channel A Request-to-Send (active low) or general purpose out-
put. If it is not used, leave it unconnected.
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