XR16L2450_05 Datasheet, PDF (18/30 Pages) Exar Corporation – 2.25V TO 5.5V DUART

XR16L2450
2.25V TO 5.5V DUART
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REV. 1.1.1
LSR[1]: Receiver Overrun Flag
• Logic 0 = No overrun error (default).
• Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens
when additional data arrives while there is data in the RHR. In this case the previous data in the receive shift
register is overwritten. Note that under this condition the data byte in the receive shift register is not
transferred into the RHR, therefore the data in the RHR is not corrupted by the error. An interrupt will be
generated immediately if LSR interrupt is enabled (IER bit-2).
LSR[2]: Receive Data Parity Error Flag
• Logic 0 = No parity error (default).
• Logic 1 = Parity error. The receive character in RHR does not have correct parity information and is suspect.
This error is associated with the character available for reading in RHR. If the LSR interrupt is enabled (IER
bit-2), an interrupt will be generated when the character is in the RHR.
LSR[3]: Receive Data Framing Error Flag
• Logic 0 = No framing error (default).
• Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with
the character available for reading in RHR. If the LSR interrupt is enabled (IER bit-2), an interrupt will be
generated when the character is in the RHR.
LSR[4]: Receive Break Flag
• Logic 0 = No break condition (default).
• Logic 1 = The receiver received a break signal (RX was a logic 0 for at least one character frame time). The
break indication remains until the RX input returns to the idle condition, “mark” or logic 1. If the LSR interrupt
is enabled (IER bit-2), an interrupt will be generated when the character is in the RHR.
LSR[5]: Transmit Holding Register Empty Flag
This bit is the Transmit Holding Register Empty indicator. This bit indicates that the transmitter is ready to
accept a new character for transmission. In addition, this bit causes the UART to issue an interrupt to the host
when the THR interrupt enable is set. The THR bit is set to a logic 1 when the data byte is transferred from the
transmit holding register to the transmit shift register. The bit is reset to logic 0 concurrently with the data
loading to the transmit holding register by the host.
LSR[6]: THR and TSR Empty Flag
This bit is set to a logic 1 whenever the transmitter goes idle. It is set to logic 0 whenever either the THR or
TSR contains a data character.
LSR[7]: Reserved
4.8 Modem Status Register (MSR) - Read Only
This register provides the current state of the modem interface signals, or other peripheral device that the
UART is connected. Lower four bits of this register are used to indicate the changed information. These bits
are set to a logic 1 whenever a signal from the modem changes state. These bits may be used as general
purpose inputs/outputs when they are not used with modem signals.
MSR[0]: Delta CTS# Input Flag
• Logic 0 = No change on CTS# input (default).
• Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
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