XR28V384 Datasheet, PDF (27/42 Pages) Exar Corporation – 3.3V QUAD LPC UART WITH 128-BYTE FIFO

XR28V384
REV. 1.0.0
3.3V QUAD LPC UART WITH 128-BYTE FIFO
Bits [3:0]: Select the IRQ channel for watchdog timer
After power on or reset, if the pin DTRC#/PS_WDT is sampled HIGH, this byte will be set to 0x00. Otherwise,
this byte will be set to 0x0. See Table 1 ’UART Power On Configuration’.
Bit [4]: Enable/Disable the watchdog timer IRQ
x Logic 0 = Disable the watchdog timer IRQ (default).
x Logic 1 = Enable the watchdog timer IRQ.
Bits [7:5]: Reserved
2.1.2.2.4
WDT Timer Status and Control Register - Read/Write
This register sets timer status and control timer events.
Bit [0]: Time Out Events
x Logic 0 = No time out occurred (default).
x Logic 1 = Time out occurred. Write ’1’ to this bit will clear the status.
Bits [2:1]: WDT Interval
x ’00’ = Timer unit is 10 ms.
x ’01’ = Timer unit is 1 second.
x ’10’ = Timer unit is 1 minute.
x ’11’ = Reserved.
Bits [7:3]: Reserved
2.1.2.2.5
WDT Count Register - Read/Write
This register programs the count value for watchdog timer.
Bits [7:0]: Sets count value for watchdog timer
Writing a non-zero value to this register once will disable the timer and writing the same value again will
enable the timer. After power on or reset, if the pin DTRC#/PS_WDT is sampled HIGH, this byte will be set to
0x0A. Otherwise, this byte will be set to 0x00. See Table 1 ’UART Power On Configuration’.
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