XR28V384 Datasheet, PDF (25/42 Pages) Exar Corporation – 3.3V QUAD LPC UART WITH 128-BYTE FIFO

XR28V384
REV. 1.0.0
3.3V QUAD LPC UART WITH 128-BYTE FIFO
2.1.2.1.5
Infrared Mode Control Register - Read/Write
The V384 supports IR mode for UART channel A only. It controls infrared mode by setting this register. See
’Section 1.4.6, Infrared Mode’.
Bit [0]: IR mode IRRXA# invert
x Logic 0 = IRRA# idles LOW. (Default)
x Logic 1 = Invert the IRRXA# for IR mode, idle at HIGH.
Bit [1]: IR mode IRTXA# invert
x Logic 0 = IRTXA# idles LOW. (Default)
x Logic 1 = Invert the IRTXA# for IR mode, idle at HIGH.
Bit [2]: IR mode Half-Duplex
x Logic 0 = Enable full duplex function for IR mode.
x Logic 1 = Enable half duplex function for IR mode (default).
Bits [4:3]: IR mode Enable
x ’00’ or ’01’ = Disable the IR function (default value is ’00’).
x ’10’ = Enable the IR function, active pulse is 1.6 us.
x ’11’ = Enable the IR function, active pulse is 3/16 bit time.
Bits [7:5]: Reserved
2.1.2.1.6
9-bit Mode Slave Address Register - Read/Write
This register indicates the slave address in 9-bit mode. This register along with the 9-bit mode slave address
mask register will determine the given address and broadcast address in 9-bit mode. The V384 will respond to
both the given address and the broadcast address.
2.1.2.1.7
9-bit Mode Slave Address Mask Register - Read/Write
This register indicates the slave address mask in 9-bit mode. This register along with the 9-bit mode slave
address register will determine the given address and broadcast address in 9-bit mode. The V384 will respond
to both the given address and the broadcast address.
x Given address: If bit n of the 9-bit mode slave address mask register is ’0’, then the corresponding bit of
given address is ’do not care’.
x Broadcast address: If bit n of the ORed 9-bit mode slave address register and 9-bit mode slave address
mask register is ’0’, then this bit n is a ’do not care’ bit. The remaining bit which is ’1’ is compared to the
received address.
TABLE 9: EXAMPLE
REGISTER
EXAMPLE 1
EXAMPLE 2
EXAMPLE 3
EXAMPLE 4
9-bit mode slave address register (0xF4)
9-bit mode slave address mask register (0xF5)
11110100
01010101
00001111
10101010
01010101
11111111
11100111
00001111
Given address
Broadcast address
x1x1x1x0
1111x1x1
0x0x1x1x
1x1x1111
01010101
11111111
xxxx0111
111x1111
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