XR20M1172_09 Datasheet, PDF (26/58 Pages) Exar Corporation – TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO

XR20M1172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO
.
REV. 1.0.1
TABLE 8: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDR
REG
NAME
READ/
WRITE
BIT-7
BIT-6
BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0
COMMENT
16C550 Compatible Registers
0x00 RHR
RD Bit-7
Bit-6
Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
0x00 THR
WR Bit-7
Bit-6
Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
0x01
IER RD/WR 0/
0/
0/
0/ Modem RX Line TX RX Data
CTS Int. RTS Int.
Enable Enable
Xoff Int.
Enable
Sleep
Mode
Enable
Stat. Int. Stat. Int. Empty
Enable Enable Int
Enable
Int.
Enable
0x02 ISR
RD FIFOs FIFOs
0/
0/
INT
INT
INT
INT
Enabled Enabled
Source Source Source Source
INT
INT
Bit-3 Bit-2 Bit-1 Bit-0
Source Source
Bit-5 Bit-4
LCR[7]=0
0x02 FCR
WR RXFIFO RXFIFO 0/
0/
DMA TX FIFO RX FIFO FIFOs
Trigger
Trigger
Mode
TXFIFO TXFIFO _Enable
Trigger Trigger
Reset
Reset Enable
0x03
0x04
LCR
MCR
RD/WR Divisor
Enable
Set TX Set Par- Even
Break
ity
Parity
Parity Stop Bits Word
Enable
Length
Bit-1
Word
Length
Bit-0
RD/WR 0/
Clock
Pres-
caler
Select
0/
IR Mode
0/
XonAny
Internal
Lopback
Enable
OP2#/
0/
INT Out-
put ^Enable
Enable ^TCR
and TLR
RTS#
Output
Control
DTR#
Output
Control
LCR≠0xBF
0x05 LSR
RD RX FIFO THR &
Global TSR
Error Empty
THR
Empty
RX
RX
RX
RX RX Data
Break Framing Parity Overrun Ready
Error Error Error
0x06 MSR
RD
CD# RI# Input DSR#
Input
Input
CTS#
Input
Delta
CD#
Delta
RI#
Delta
DSR#
Delta
CTS#
See Table 12
0x07 SPR RD/WR Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2 Bit-1 Bit-0 See Table 13
0x06
TCR RD/WR Resume Resume Resume Resume Halt
Bit-3
Bit-2
Bit-1 Bit-0
Bit-3
Halt
Bit-2
Halt
Bit-1
Halt
See Table 12
Bit-0
0x07
TLR
RD/WR RX Trig
Bit-3
RX Trig
Bit-2
RX Trig
Bit-1
RX Trig
Bit-0
TX Trig
Bit-3
TX Trig
Bit-2
TX Trig
Bit-1
TX Trig
Bit-0
See Table 13
0x08 TXLVL RD/WR 0
Bit-6
Bit-5 Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
0x09 RXLVL RD/WR 0
Bit-6
Bit-5 Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
0x0A IODir RD/WR Bit-7
Bit-6
Bit-5 Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
26