XRP7713_10 Datasheet, PDF (23/29 Pages) Exar Corporation – Three Channel Digital PWM Step Down Controller

XRP7713
Three Channel Digital PWM Step Down Controller
CLK_IN
GPIO3
CLK_OUT
GPIO1
GPIO2 ^SYNC_OUT
XRP7713
Configured as a
master with
external clock sync
CLK_IN
GPIO1
SYNC_IN
GPIO2
XRP7713
configured
as slave
Fig. 291: Alternative External clock synchronization Master Slave combination
PHASE SHIFT
Each switching channel is configured to run with a phase shift of 90 degrees.
GPIO PINS
The General Purpose Input Output (GPIO) Pins are the basic interface between the XRP7713 and
the system. Although all of the stored data within the IC can be read back using the I2C bus it is
sometimes convenient to have some of those internal register to be displayed and or controlled by
a single data pin. Besides simple input output functions the GPIO pins can be configured to serve
as external clock inputs. These pins can be programmed using OTP bits or can be programmed
using the I²C bus. This GPIO_CONFIG register allows the user close to 100 different configuration
functions that the GPIO can be programmed to do.
NOTE: the GPIO Pins (and all I/Os) should NOT be driven without a 10K resistor when VIN is not
being applied to the IC.
GPIO Pins Polarity
The polarity of the GPIO pin can be set by using the GPIO_ACT_POL register. This register allows
any GPIO pin whether configured as an input or output to change polarity. Bits [5:0] are used to
set the polarity of GPIO 1 though 5. If the IC operates in I²C mode, then the commands for Bits
[5:4] are ignored.
Supply Rail Enable
Each GPIO can be configured to enable a specific power rail for the system. The GPIOx_CFG
register allows a GPIO to enable/disable any of the following rails controlled by the chip:
• A single buck power controller
• The Standby LDO
• Any mix of the Standby LDO and power controller(s)
When the configured GPIO is asserted externally, the corresponding rails will be enabled, and they
will be similarly disabled when the GPIO is de-asserted. This supply enabling/disabling can also be
controlled through the I²C interface.
Power Good Indicator
The GPIO pins can be configured as Power Good indicators for one or more rails. The GPIO pin is
asserted when all rails configured for this specific IO are within specified limits for regulation. This
information can also be found in the READ_PWRGD_SS_FLAG status register.
© 2010 Exar Corporation
23/29
Rev. 1.1.1