XR16V2652_07 Datasheet, PDF (22/48 Pages) Exar Corporation – HIGH PERFORMANCE DUART WITH 32-BYTE FIFO

XR16V2652
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO
.
REV. 1.0.2
TABLE 9: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS REG READ/
A2-A0 NAME WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3 BIT-2 BIT-1 BIT-0 COMMENT
16C550 Compatible Registers
0 0 0 RHR RD Bit-7 Bit-6 Bit-5 Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
0 0 0 THR WR Bit-7 Bit-6 Bit-5 Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
001
010
IER RD/WR 0/
0/
0/
0/
Modem RX Line TX
RX
CTS Int. RTS Int. Xoff Int.
Enable Enable Enable
Sleep
Mode
Enable
Stat. Int. Stat. Empty Data
Enable Int.
Int
Int.
Enable Enable Enable
ISR RD FIFOs FIFOs
0/
0/
INT
INT INT INT ^LCR[7]=0
Enabled Enabled
INT
INT
Source Source
Source Source Source Source
Bit-3 Bit-2 Bit-1 Bit-0
Bit-5 Bit-4
010
FCR
WR RXFIFO RXFIFO 0/
0/
DMA
TX
RX FIFOs
Trigger Trigger
TXFIFO TXFIFO
Trigger Trigger
Mode
Enable
FIFO FIFO Enable
Reset Reset
011
LCR RD/WR Divisor Set TX Set
Enable Break _Parity
Even
Parity
Parity
Enable
Stop
Bits
Word Word
Length Length
Bit-1 Bit-0
100
MCR RD/WR 0/
BRG
Pres-
caler
0/
IR Mode
ENable
0/
XonAny
Internal
Lopback
Enable
OP2#
Output
Control
OP1#
IR
Invert
RTS# DTR#
Output Output
Control Control
1 0 1 LSR RD RX FIFO THR & THR
RX
RX
RX
RX
RX _{LCR ≠ 0xBF}
Global TSR Empty Break _Framing Parity Over- Data
Error Empty
Error ^{Error run Ready}
Error
1 1 0 MSR RD
CD#
Input
RI#
Input
DSR#
Input
CTS#
Input
Delta
CD#
Delta Delta Delta
RI# DSR# CTS#
1 1 1 SPR RD/WR Bit-7 Bit-6 Bit-5 Bit-4
Bit-3 Bit-2 Bit-1 Bit-0 LCR ≠ 0xBF
000
001
010
010
DLL RD/WR Bit-7
DLM RD/WR Bit-7
AFR RD/WR Rsvd
DLD RD/WR 0
Baud Rate Generator Divisor
Bit-6 Bit-5 Bit-4
Bit-3
Bit-6 Bit-5 Bit-4
Bit-3
Rsvd Rsvd Rsvd Rsvd
0 4X Mode 8X Mode Bit-3
Bit-2
Bit-2
Bit-1
Bit-1
Bit-0 ^LCR[7]=1
LCR ≠ 0xBF
Bit-0
RXRDY# Baudout# Concur- LCR[7]=1
Select Select rent Write _{LCR ≠ 0xBF}
EFR[4] = 0
Bit-2
Bit-1
Bit-0
LCR[7]=1
LCR ≠ 0xBF
EFR[4] = 1
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