XRP7704 Datasheet, PDF (21/31 Pages) Exar Corporation – Quad-Output Digital PWM Buck Controller

REV 1.1.0
XRP7704
Quad-Output Digital PWM Buck Controller
Soft-Stop
The SET_PD_FALL_CHx register is a 16 bit register. This register specifies the soft-stop delay and ramp (fall-
time) characteristics for when the chip receives a channel disable indication from the Host to shutdown the
channel.
Bits [15:10] specify the delay after disabling a channel but before starting the shutdown of the channel; where
each bit represents 250us steps. Bits [9:0] specify the fall time of the channel; these 10 bits define the number of
microseconds for each 50mV increment to reach the discharge threshold.
Channel Soft-Stop Sequence
Power Good Flag
The XRP7704 allows the user to set the upper and lower bound for a power good signal per channel. The
SET_PWRG_TARG_MAX_CHx register sets the upper bound, the SET_PWRG_TARG_MIN_CHx register sets
the lower bound. Each register has a 20mV LSB resolution. When the output voltage is within bounds the power
good signal is asserted high. Typically the upper bound should be lower than the over-voltage threshold. In
addition, the power good signal can be delayed by a programmable amount set in the SET_PWRGD_DLY_CHx
register. The power good delay is only set after the soft-start period is finished. If the channel has a pre-charged
condition that falls into the power good region, a power good flag is not set until the soft-start is finished.
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