XRP7704 Datasheet, PDF (15/31 Pages) Exar Corporation – Quad-Output Digital PWM Buck Controller

REV 1.1.0
XRP7704
Quad-Output Digital PWM Buck Controller
Chip Power-Up
The figure below shows the power-up sequence of XRP7704 during the normal operation. The startup stage is
divided into three phases. The first phase is the internal LDO power-up phase. The second phase is the
configuration transfer phase. The third phase is chip ready phase. The power up sequence is less than 1ms.
Phase 1
Phase 2
Phase 3
VIN1
ENABLE_PIN
VCC
VDD
VDDOK
SYS_RESET
CONFIG_TRANSFER
CHIP_READY
Power up sequence
Internal LDO Power-Up Phase – Phase 1
When the ENABLE pin is set, internal VCC and VDD power up upon the power up of VIN1. Once the bandgap
reference is stable and VCC and VDD fall into the acceptable range, an internal VDDOK flag is generated. A
SYS_RESET remains low for a few clock cycles to reset all the internal registers. After that the internal
CONFIGURATION_TRANSFER signal raises high and the chip transits to the second phase.
Configuration Transfer Phase – Phase 2
In this phase, the contents in the configuration memory are transferred to the internal registers. The internal
oscillator switches to the programed switching frequency. The GPIO pins are properly configured as either inputs
or outputs. If the chip is programmed to run in the I²C mode, GPIO4 and GPIO5 are configured to serve as SDA
and SCL for the I²C bus. If chip is programmed to run in the NON-I²C mode, then these two pins can be used as
GPIO4 and GPIO5 respectively.
Chip Ready Phase – Phase 3
In this phase, the chip is ready for normal operation. An internal CHIP_READY flag goes high and enables the I²C
to acknowledge the Host’s serial commands. Channels that are configured as always-on channels are enabled.
Channels that are configured to be enabled by GPIOs are also enabled if the respective GPIO is asserted.
EXAR CONFIDENTIAL. PROPRIETARY. DO NOT DISTRIBUTE OR COPY.
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