DAN-176 Datasheet, PDF (2/5 Pages) Exar Corporation – POWER-SAVE FEATURE: SLEEP CURRENT DOWN

DATA COMMUNICATIONS APPLICATION NOTE
DAN176
4.0 POWER STATES
The Sleep, Power-Save as well as the Normal operating states of the Low Power UART are shown in Figure 2.
The figure also shows the conditons under which the transitions between these power states take place. Since
the internal registers of the device cannot be accessed while in Power-Save mode, the system design engi-
neer must use caution if he/she is planning to use this feature. The device will emerge from the Power-Save
mode only by an external event, namely activity on the RX pin or one of the other modem input pins, namely
CTS#, DSR#, CD# or RI#. It is highly recommended that the PwrSave pin of the device be controlled by an I/O
pin available in the system which can be controlled via software. This will provide a mechanism to access the
Low Power UART, in case the external event does not occur to wake up the UART. Figure 3 shows an applica-
tion example when the PwrSave pin of the device is controlled via an I/O pin of the system.
FIGURE 2. VARIOUS POWER STATES OF THE LOW POWER UART
Normal Operating State
with
PwrSave = LOW
PwrSave = HIGH
PwrSave = LOW
Normal Operating State
with
PwrSave = HIGH
CPU/FPGA can control the
PwrSave pin via a general-purpose
I/O pin
Sleep State
PwrSave = LOW
Power-Save State
PwrSave = HIGH
Condition A: RX pin goes LOW OR Any of the delta bits in MSR
register is set
Condition B: Condition A OR Transmitter not empty
Condition C: Condition B has been serviced
2