DAN-173 Datasheet, PDF (2/3 Pages) Exar Corporation – UPGRADING FROM XR88C681 TO XR88C92/192

DATA COMMUNICATIONS APPLICATION NOTE
DAN173
3.3 MASKED INTERRUPT STATUS REGISTER MISR:
This register ANDs the values of the write-only Interrupt Mask Register (IMR) and the Interrupt Status Register
(ISR) together.
MISR value = [ISR value] * [IMR value]
In the C92/192, the user needs to store the value written into the IMR and do the ANDing operation in software.
3.4 COMMAND REGISTER (CRA, CRB) DIFFERENCES:
The upper nibble of the Command Register in both the C681 and the C92/192 is used to issue various com-
mands. While many of the commands are the same, some are different as shown in Table 2 below:
TABLE 2: COMMANDS DESCRIPTION DIFFERENCES BETWEEN THE XR88C681 AND XR88C92/192
COMMAND REGISTER
BITS 7:4
1000
1001
1010
1011
1100
1101
1110
1111
XR88C681
Set RX BRG Select Extend Bit
Clear RX BRG Select Extend Bit
Set TX BRG Select Extend Bit
Clear TX BRG Select Extend Bit
Set Standby Mode (Channel A)
Reset IUS Latch (Channel B)
Set Active Mode (Channel A)
Set Z-Mode (Channel B)
Not used
Not used
XR88C92/192
Set -RTS output to LOW (Assertion)
Set -RTS output to HIGH (Negation)
Enable Time-out Mode
Set Mode Register Pointer to MR0
Disable Time-out Mode
Not used
Enable Power Down Mode (Channel A only)
Disable Power Down Mode (Channel A only)
3.5 RECEIVE TRIGGER LEVELS:
The C681 provides a choice of generating a Receive Ready interrupt either for each character received or
when the RX FIFO is full (via MR1 bit-6). The C92/192 combines this bit and the new MR0 bit-6 to provide four
RX trigger levels as follows:
RX TRIGGER LEVELS IN
MR0 BIT-6 MR1 BIT-6
XR88C92 (8-BYTE FIFO) XR88C192 (16-BYTE FIFO)
0
0
0
1
1
0
1
1
1 byte in FIFO
3 bytes in FIFO
6 bytes in FIFO
8 bytes in FIFO
1 byte in FIFO
6 bytes in FIFO
12 bytes in FIFO
16 bytes in FIFO
3.6 TRANSMIT TRIGGER LEVELS:
The C681 generates a Transmit Ready interrupt only when the transmit FIFO is empty. The C92/192 via the
MR0 register bits 4 and 5 provides four TX trigger levels as shown in the table below:
TX TRIGGER LEVELS IN
MR0 BIT-5 MR0 BIT-4
XR88C92 (8-BYTE FIFO) XR88C192 (16-BYTE FIFO)
0
0
FIFO Fully Empty
FIFO Fully Empty
0
1
4 FIFO locations empty 6 FIFO locations empty
1
0
6 FIFO locations empty 12 FIFO locations empty
1
1
1 FIFO location empty
1 FIFO location empty
2