XR8051 Datasheet, PDF (19/27 Pages) Exar Corporation – Low Cost, High Speed Rail-to-Rail Amplifiers

For a given load capacitance, adjust R_S to optimize the
tradeoff between settling time and bandwidth. In general,
reducing R_S will increase bandwidth at the expense of
additional overshoot and ringing.
Layout Considerations
General layout and supply bypassing play major roles in
high frequency performance. Exar has evaluation boards to
use as a guide for high frequency layout and as an aid in
device testing and characterization. Follow the steps below
as a basis for high frequency layout:
■■ Include 6.8µF and 0.1µF ceramic capacitors for power supply
decoupling
■■ Place the 6.8µF capacitor within 0.75 inches of the power pin
■■ Place the 0.1µF capacitor within 0.1 inches of the power pin
■■ Remove the ground plane under and around the part,
especially near the input and output pins to reduce parasitic
capacitance
■■ Minimize all trace lengths to reduce series inductances
Refer to the evaluation board layouts below for more
information.
Evaluation Board Information
The following evaluation boards are available to aid in the
testing and layout of these devices:
Evaluation Board #
CEB002
CEB003
CEB006
CEB010
CEB018
Products
XR8051 in TSOT
XR8051 in SOIC
XR8052 in SOIC
XR8052 in MSOP
XR8054 in TSSOP
Evaluation Board Schematics
Evaluation board schematics and layouts are shown in
Figures 8-14 These evaluation boards are built for dual-
supply operation. Follow these steps to use the board in a
single-supply application:
1. Short -V_S to ground.
2. Use C3 and C4, if the -V_S pin of the amplifier is not
directly connected to the ground plane.
XR8051, XR8052, XR8054
Figure 8. CEB002 & CEB003 Schematic
Figure 9. CEB002 Top View
© 2007-2014 Exar Corporation
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exar.com/XR8051
Rev 1B