SP505 Datasheet, PDF (19/35 Pages) Sipex Corporation – WAN Multi-Mode Serial Transceiver

Phase 2 (±10V)
— V_SS transfer — Phase two of the clock
connects the negative terminal of C₂ to
the V_SS storage capacitor and the positive
terminal of C₂ to ground, and transfers the
generated –l0V or the generated –5V to C₃.
Simultaneously, the positive side of capacitor
C ₁ is switched to +5V and the negative side
is connected to ground.
Phase 2 (±5V)
— V_SS & V_DD charge storage — C₁₊ is recon-
nCe₂₊citsesdwtiotcVhe_CCd
to
to
grerocuhnadrgaendthCe_2–^Cis1
capacitor.
connected
to C₃. The 5V charge from Phase 1 is now
transferred to the V_SS storage capacitor. V_SS
receives a continuous charge from either C₁
or C₂. With the C1 capacitor charged to 5V,
the cycle begins again.
Phase 3
— V_DD charge storage — The third phase
of the clock is identical to the first phase
— the charge transferred in C₁ produces
–5V in the negative terminal of C₁, which
is applied to the negative side of capacitor
C₂. Since C₂₊
across C₂ is
is at
l0V.
+5V, the
For the
voltage potential
5V output, C₂₊ is
connected to ground so that the potential
on C₂ is only +5V.
Phase 4
— V_DD transfer — The fourth phase of the
clock connects the negative terminal of C₂
to ground and transfers the generated l0V
or the generated 5V across C₂ to C₄, the V_DD
storage capacitor. Again, simultaneously
with this, the positive side of capacitor C₁
is switched to +5V and the negative side is
connected to ground, and the cycle begins
again.
Since both V_DD and V_SS are separately gen-
erated from V_CC in a no–load condition, V_DD
and V_SS will be symmetrical. Older charge
pump approaches that generate V^– from
V⁺ will show a decrease in the magnitude
of V^– compared to V⁺ due to the inherent
inefficiencies in the design.
The clock rate for the charge pump typically
operates at 15kHz. The external capacitors
must be a minimum of 22µF with a 16V
breakdown rating.
External Power Supplies
For applications that do not require +5V
only, external supplies can be applied at the
V+ and V^– pins. The value of the external
supply voltages must be no greater than
+l0.5V. The tolerance should be +5% from
+10V. The current drain for the supplies is
used for RS-232 and RS-423 drivers. For
the RS-232 driver, the current requirement
will be 3.5mA per driver. The RS-423 driver
worst case current drain will be 11mA per
driver. Power sequencing is required for the
SP505. The supplies must be sequenced
accordingly: +10V, +5V and –10V. It is
important to prevent V_SS from starting up
before V_CC or V_DD.
V CC = +5V
+
C_{1 –}
+
C_{2 –}
–1 0V
C4
+ – V _DD S torage C apa citor
– + _{VSS S torage C apa citor}
C3
Figure 47. Charge Pump Phase 2 for +10V.
V CC = +5V
+
C_{1 –}
+
C_{2 –}
–5 V
C4
+ – V _DD S torage C apa citor
– + _{VSS S torage C apa citor}
C3
Figure 48. Charge Pump Phase 2 for +5V.
V CC = +5V
+
C_{1 –}
–5 V
+5V
+
C_{2 –}
–5 V
C4
+ – V _DD S torage C apa citor
– + _{VSS S torage C apa citor}
C3
Figure 49. Charge Pump Phase 3.
V CC = +5V
+
C_{1 –}
+10V
+
C_{2 –}
C4
+ – V _DD S torage C apa citor
– + _{VSS S torage C apa citor}
C3
Figure 50. Charge Pump Phase 4.
Exar Coporation 48720 Kato Road, Fremont CA, 94538 • [phone] • Fax [phone] • www.exar.com
19
SP505_100_081308