SP330EEY-L Datasheet, PDF (18/23 Pages) Exar Corporation – SP330E RS-232/RS-485/RS-422 TRANSCEIVER WITH 1.65V-5.5V INTERFACE

SP330E
RS-232/RS-485/RS-422 TRANSCEIVER WITH 1.65V-5.5V INTERFACE
PRODUCT SUMMARY
REV. 1.0.0
The SP330 is an advanced multiprotocol transceiver supporting RS-232, RS-485, and RS-422 serial
standards. The multiple configuration modes allow all three protocols to be used interchangeably over a single
cable or connector with no additional switching components. Full operation requires only four external charge
pump capacitors.
ENHANCED FAILSAFE
The enhanced failsafe feature of the SP330 guarantees a logic-high receiver output when the receiver inputs
are open, shorted, or terminated but idle/undriven. The enhanced failsafe interprets 0V differential as a logic
high with a minimum 50mV noise margin, while maintaining compliance with the EIA/TIA-485 standard of
±200mV. No external biasing resistors are required, further easing the usage of multiple protocols over a single
connector.
±15kV ESD PROTECTION
ESD protection structures are incorporated on all pins to protect against electrostatic discharges encountered
during handling and assembly. The bus pins (driver outputs and receiver inputs) have extra protection
structures, which have been tested up to ±15kV without damage. These structures withstand high ESD in all
states: normal operation, in shutdown, and when powered off.
ESD protection is be tested in various ways. Exar uses the following methods to qualify the protection
structures designed into SP330:
±8kV using IEC 61000-4-2 Contact Discharge
±15kV using IEC 61000-4-2 Airgap Discharge
±15kV using the Human Body Model (HBM)
The IEC 61000-4-2 standard is more rigorous than HBM, resulting in lower voltage levels compared with HBM
for the same level of ESD protection. Because IEC 61000-4-2 specifies a lower series resistance, the peak
current is higher than HBM. The SP330 has passed both HBM and IEC 61000-4-2 testing without damage.
VARIABLE LOGIC LEVEL VOLTAGE
The SP330 includes a V_L pin which reduces the logic level thresholds to interface with processors operating at
reduced supply voltages. This pin should be connected to the supply voltage of the processor or UART block,
or can be connected to V_CC for typical logic levels.
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