XR215A Datasheet, PDF (17/32 Pages) Exar Corporation – Monolithic Phase-Locked Loop

XR-215A
Os
-
O0
K_d
F(s)
Ko
s
Figure 14. Linearized Model of a PLL as a
Negative Feedback System
Phase Comparator Gain K_d
The output voltage from the phase comparator per radian
of phase difference at the phase comparator inputs (pins
4 and 6). The units are volts/radians. (See Figure 9.)
VCO Conversion Gain Ko
The VCO voltage-to-frequency conversion gain is
determined by the choice of timing capacitor C₀ and gain
control resistor, R₀ connected externally across pins 11
and 12. It can be expressed as:
K₀
[
700 _{(radians/sec/volt)}
C₀R₀
where C₀ is in mF and R₀ is in kW. For most applications,
recommended values for R₀ range from 1kW to 10kW.
Lock Range (DwL)
The range of frequencies in the vicinity of f_o, over which
the PLL can maintain lock with an input signal. It is also
known as the “tracking” or “holding” range. If saturation or
limiting does not occur, the lock range is equal to the loop
gain, i.e. Dw_L = K_T = K_dK_o.
Capture Range (DwC)
The band of frequencies in the vicinity of f_o where the PLL
can establish or acquire lock with an input signal. It is also
known as the “acquisition” range. It is always smaller than
the lock range and is related to the low-pass filter
bandwidth. It can be approximated by a parametric
equation of the form:
Dw_C  Dw_L |F(jDw_C)|
where |F(jDw_C| is the low-pass filter magnitude response
at w = Dw_C. For a simple lag filter, it can be expressed as:
Ǹ Dw_C [
Dw_L
T₁
where T₁ is the filter time constant.
Amplifier Gain AV
The voltage gain of the amplifier section is determined by
feedback resistors R_F and Rp between pins (8,1) and
(2,1) respectively. (See Figure 3 and Figure 4.) It is given
by:
A_V [
–R_F
R₁ ) R_P
where R₁ is the (6kW) internal impedance at pin 2.
Rev. 1.01
17