XR16C850_05 Datasheet, PDF (17/56 Pages) Exar Corporation – 2.97V TO 5.5V UART WITH 128-BYTE FIFO

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REV. 2.3.1
FIGURE 11. RECEIVER OPERATION IN NON-FIFO MODE
XR16C850
2.97V TO 5.5V UART WITH 128-BYTE FIFO
16X Clock
Receive Data Shift Data Bit
Register (RSR)
Validation
Receive Data Characters
Receive
Data Byte
and Errors
Error
Tags in
LSR bits
4:2
Receive Data
Holding Register
(RHR)
RHR Interrupt (ISR bit-2)
RXFIFO1
FIGURE 12. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE
16X Clock
128 bytes by 11-bit
wide
FIFO
Receive Data
Byte and Errors
Receive Data Shift
Register (RSR)
Receive
Data FIFO
Receive
Data
Data Bit
Validation
Receive Data Characters
E xam p le
- :RX FIFO trigger level selected at 16
bytes
Data falls to
8
(See Note Below)
RTS# re-asserts when data falls below the flow
control trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
FIFO
Trigger=16
RHR Interrupt (ISR bit-2) programmed for
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1
Data fills to
24
RTS# de-asserts when data fills above the flow
control trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
RXFIFO1
NOTE: Table-B selected as Trigger Table for Figure 12 (Table 10).
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