XR16C850_05 Datasheet, PDF (11/56 Pages) Exar Corporation – 2.97V TO 5.5V UART WITH 128-BYTE FIFO

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REV. 2.3.1
XR16C850
2.97V TO 5.5V UART WITH 128-BYTE FIFO
2.3 16-Bit Bus Interface
The 16-bit bus interface is only available on the 48 pin package. The 16-bit bus mode is enabled when the
BUS8/16 pin is connected to GND. In this mode, the RX data errors can be read via the higher order data bus
pins D10-D12. See Figure 6.
FIGURE 6. XR16C850 16-BIT BUS INTERFACE
D0
D1
D2
D3
D4
D5
D6
D7
Parity Error
Framing Error
Break Error
A0
A1
A2
IOR
IOW
CS#
INT
RESET
D0
D1
D2
D3
D4
D5
D6
D7
D10
D11
D12
A0
A1
A2
IOR#
IOW #
BAUDOUT#
RCLK
VCC
CS0
CS1
SEL
TX
RX
DTR#
RTS#
CTS#
DSR#
CD#
RI#
CS2#
OP1#
OP2#
INT
RESET
BUS8/16
IOW
IOR
AS#
GND
VCC
2.4 5-Volt Tolerant Inputs
For devices that have top mark date code "F2 YYWW" and newer, the 850 can accept a voltage of up to 5.5V
on any of its inputs (except XTAL1) when operating from 2.97V to 5.5V. XTAL1 is not 5 volt tolerant. Devices
that have top mark date code "EC YYWW" and older do not have 5V tolerant inputs.
2.5 Device Reset
The RESET input resets the internal registers and the serial interface outputsto their default state (see
Table 15). An active high pulse of longer than 40 ns duration will be required to activate the reset function in
the device.
2.6 Device Identification and Revision
The XR16C850 provides a Device Identification code and a Device Revision code to distinguish the part from
other devices and revisions. To read the identification code from the part, it is required to set the baud rate
generator registers DLL and DLM both to 0x00. Now reading the content of the DLM will provide 0x10 for the
XR16C850 and reading the content of DLL will provide the revision of the part; for example, a reading of 0x01
means revision A.
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