XRT86VL32 Datasheet, PDF (160/173 Pages) Exar Corporation – DUAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

xr
REV. P1.0.5
PRELIMINARY
XRT86VL32
DUAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
TABLE 121: LIU CHANNEL CONTROL STATUS REGISTER (LIUCCSR)
HEX ADDRESS: 0X0FN5
BIT
FUNCTION
TYPE DEFAULT
DESCRIPTION-OPERATION
2
Reserved
-
0
This Bit Is Not Used
1
RLOS_n
RO
0
Receive Loss of Signal Defect Condition Status:
This READ-ONLY bit indicates whether or not the Receive LIU Block
is currently declaring the LOS defect condition.
0 = Indicates that the Receive Section is NOT currently declaring
the LOS Defect Condition.
1 = Indicates that the Receive Section is currently declaring the LOS
Defect condition.
NOTE: If the RLOSIE bit (bit D1 of Register 0x0Fn4) is enabled, any
transition on this bit will generate an Interrupt.
0
QRPD_n
RO
0
Quasi-random Pattern Detection Status:
This READ-ONLY bit indicates whether or not the Receive LIU Block
is currently declaring the QRSS Pattern LOCK status.
0 = Indicates that the XRT86VL32 is NOT currently declaring the
QRSS Pattern LOCK.
1 = Indicates that the XRT86VL32 is currently declaring the QRSS
Pattern LOCK.
NOTE: If the QRPDIE bit (bit D0 of register 0x0Fn4) is enabled, any
transition on this bit will generate an Interrupt.
155