XRT86VL32 Datasheet, PDF (120/173 Pages) Exar Corporation – DUAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

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REV. P1.0.5
PRELIMINARY
XRT86VL32
DUAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
TABLE 100: DATA LINK INTERRUPT ENABLE REGISTER 1 (DLIER1)
HEX ADDRESS: 0XnB07
BIT
FUNCTION
TYPE DEFAULT
DESCRIPTION-OPERATION
2 FCS ERR ENB
R/W
0
FCS Error Interrupt Enable
This bit enables or disables the “Received FCS Error “Interrupt
within the XRT86VL32 device. Once this interrupt is enabled, the
Receive HDLC1 Controller will generate an interrupt when it has
detected the FCS error within the incoming data link message.
0 = Disables the “Receive FCS Error” interrupt.
1 = Enables the “Receive FCS Error” interrupt.
1 RxABORT ENB
R/W
0
Receipt of Abort Sequence Interrupt Enable
This bit enables or disables the “Receipt of Abort Sequence“ Inter-
rupt within the XRT86VL32 device. Once this interrupt is enabled,
the Receive HDLC1 Controller will generate an interrupt when it has
detected the Abort Sequence (i.e. a string of seven (7) consecutive
1’s) within the incoming data link channel.
0 = Disables the “Receipt of Abort Sequence” interrupt.
1 = Enables the “Receipt of Abort Sequence” interrupt.
0 RxIDLE ENB
R/W
0
Receipt of Idle Sequence Interrupt Enable
This bit enables or disables the “Receipt of Idle Sequence“ Interrupt
within the XRT86VL32 device. Once this interrupt is enabled, the
Receive HDLC1 Controller will generate an interrupt when it has
detected the Idle Sequence Octet (i.e. 0x7E) within the incoming
data link channel.
0 = Disables the “Receipt of Idle Sequence” interrupt.
1 = Enables the “Receipt of Idle Sequence” interrupt.
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