XR21V1414 Datasheet, PDF (15/26 Pages) Exar Corporation – 4-CH FULL-SPEED USB UART

XR21V1414
REV. 1.0.0
4-CH FULL-SPEED USB UART
3.0 REGISTER SET DESCRIPTION
The internal register set of the V1414 consists of 2 different types of registers: UART Manager and UART
registers. The UART Manager controls the TX, RX and FIFOs of all UART channels. The UART registers
configure and control the remaining UART channel functionality not related to the UART FIFO.
3.1 UART Manager Registers..
TABLE 5: UART MANAGER REGISTERS
ADDRESS
REGISTER NAME
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
0X10 FIFO_ENABLE_CHA
0
0
0
0
0
0
RX
TX
0X11 FIFO_ENABLE_CHB
0
0
0
0
0
0
RX
TX
0X12 FIFO_ENABLE_CHC
0
0
0
0
0
0
RX
TX
0x13 FIFO_ENABLE_CHD
0
0
0
0
0
0
RX
TX
0X18 RX_FIFO_RESET_CHA Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0X19 RX_FIFO_RESET_CHB Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0x1A RX_FIFO_RESET_CHC Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0x1B RX_FIFO_RESET_CHD Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0x1C TX_FIFO_RESET_CHA Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0x1D TX_FIFO_RESET_CHB Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0x1E TX_FIFO_RESET_CHC Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0x1F TX_FIFO_RESET_CHD Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
FIFO_ENABLE Registers
Enables the RX FIFO and TX FIFOs. For proper functionality, the UART TX and RX must be enabled in the
following order:
FIFO_ENABLE_CHx = 0x1 // Enable TX FIFO
UART_ENABLE = 0x3
// Enable TX and RX of that channel
FIFO_ENABLE_CHx = 0x3 // Enable RX FIFO
RX_FIFO_RESET and TX_FIFO_RESET Registers
Writing a non-zero value to these registers resets the FIFOs.
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