XR21V1414 Datasheet, PDF (12/26 Pages) Exar Corporation – 4-CH FULL-SPEED USB UART

XR21V1414
4-CH FULL-SPEED USB UART
REV. 1.0.0
1.4.5 Automatic DTR/DSR Hardware Flow Control
Auto DTR/DSR hardware flow control behaves the same as the Auto RTS/CTS hardware flow control
described above except that it uses the DTR# and DSR# signals. For Auto hardware flow control,
FLOW_CONTROL[2:0] = ’001’. GPIO3 and GPIO2 become DTR# and DSR#, respectively, when
GPIO_MODE[2:0] = ’010’.
1.4.6 Automatic XON/XOFF Software Flow Control
When software flow control is enabled, the V1414 compares the receive data characters with the programmed
Xon or Xoff characters. If the received character matches the programmed Xoff character, the V1414 will halt
transmission as soon as the current character has completed transmission. Data transmission is resumed
when a received character matches the Xon character. Software flow control is enabled when
FLOW_CONTROL[2:0] = ’010’.
1.4.7 Multidrop Mode with Automatic Half-Duplex Transceiver Control
Multidrop mode with Automatic Half-Duplex Transceiver Control is enabled when GPIO_MODE[2:0] = ’011’
and FLOW_CONTROL[2:0] = ’011’.
1.4.7.1 Receiver
In this mode, the UART Receiver will automatically be enabled when an address byte (9th bit or parity bit is ’1’)
is received that matches the value stored in the XON_CHAR or XOFF_CHAR register. The address byte will
not be loaded into the RX FIFO. All subsequent data bytes will be loaded into the RX FIFO. The UART
Receiver will automatically be disabled when an address byte is received that does not match the values in the
XON_CHAR or XOFF_CHAR register.
1.4.7.2 Transmitter
GPIO5/RTS# pin behaves as control pin for the direction of a half-duplex RS-485 transceiver. The polarity of
the GPIO5/RTS# pin can be configured via GPIO_MODE[3]. When the UART is not transmitting data, the
GPIO5/RTS# pin will be de-asserted. The GPIO5/RTS# pin will be asserted immediately before the UART
starts transmitting data. When the UART is done transmitting data, the GPIO5/RTS# pin will be de-asserted.
1.4.8 Multidrop Mode with Automatic Transmitter Enable
Multidrop mode with Automatic Transmitter Enable is enabled when GPIO_MODE[2:0] = ’100’ and
FLOW_CONTROL[2:0] = ’100’.
1.4.8.1 Receiver
The behavior of the receiver is the same in this mode as it is in the Address Match mode described above.
1.4.8.2 Transmitter
When there is an address match with the XON_CHAR register, the GPIO5/RTS# pin is asserted and remains
asserted whether the UART is transmitting data or not. The GPIO5/RTS# pin will be de-asserted when an
address byte is received that does not match the value in the XON_CHAR register. The polarity of the GPIO5/
RTS# pin can be configured via GPIO_MODE[3].
1.4.9 Programmable Turn-Around Delay
By default, the GPIO5/RTS# pin will be de-asserted immediately after the stop bit of the last byte has been
shifted. However, this may not be ideal for systems where the signal needs to propagate over long cables.
Therefore, the de-assertion of GPIO5/RTS# pin can be delayed from 1 to 15 bit times via the
XCVR_EN_DELAY register to allow for the data to reach distant UARTs.
1.4.10 Half-Duplex Mode
Half-duplex mode is enabled when FLOW_CONTROL[3] = 1. In this mode, the UART will ignore any data on
the RX input when the UART is transmitting data.
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