XR-2211A Datasheet, PDF (15/24 Pages) Exar Corporation – FSK Demodulator/ Tone Decoder

2
0.1µF
Tone
Input
XR-2211A
V_CC
Loop
11
Phase
Detect
VCO
8
C22_10pF
5%
12
R₁
200K
1%
10
0.1µF
14
13
C₀
50nF
5%
R₀
20K
1%
Rx
5K
VCO
Fine
Tune
Quad
Phase
Detect
3
R_D
470K
C_D
80nF
7
FSK
Comp.
Internal
Reference
V_CC
RL2
5.1K
6 LDOQ
5 LDOQN
Lock
Detect
Comp.
RL3
5.1K
Logic Output
Figure 12. Circuit Connection for Tone Detection
FSK Decoding with Carrier Detect
The lock detect section of XR-2211A can be used as a
carrier detect option for FSK decoding. The
recommended circuit connection for this application is
shown in Figure 11. The open collector lock detect output,
pin 6, is shorted to data output (pin 7). Thus, data output
will be disabled at “low” state, until there is a carrier within
the detection band of the PLL and the pin 6 output goes
“high” to enable the data output.
Note: Data Output is “Low” When No Carrier is Present.
The minimum value of the lock detect filter capacitance
C_D is inversely proportional to the capture range, +Dfc.
This is the range of incoming frequencies over which the
loop can acquire lock and is always less than the tracking
range. It is further limited by C₁. For most applications, Dfc
> Df/2. For R_D = 470KW, the approximate minimum value
of C_D can be determined by:
C_D
§
16
Df
C in mF and f in Hz.
C in mF and f in Hz.
With values of C_D that are too small, chatter can be
observed on the lock detect output as an incoming signal
frequency approaches the capture bandwidth.
Excessively large values of C_D will slow the response time
of the lock detect output. For Caller I.D. applications
choose C_D = 0.1mF.
Tone Detection
Figure 12. shows the generalized circuit connection for
tone detection. The logic outputs, LDOQN and LDOQ at
pins 5 and 6 are normally at “high” and “low” logic states,
respectively. When a tone is present within the detection
band of the PLL, the logic state at these outputs become
reversed for the duration of the input tone. Each logic
output can sink 5mA of load current.
Both outputs at pins 5 and 6 are open collector type
stages, and require external pull-up resistors R_L2 and
R_L3, as shown in Figure 12.
With reference to Figure 3. and Figure 12., the functions
of the external circuit components can be explained as
follows: R₀ and C₀ set VCO center frequency; R₁ sets the
detection bandwidth; C₁ sets the low pass-loop filter time
constant and the loop damping factor.
Rev. 1.01
15