XRT86L30_07 Datasheet, PDF (147/279 Pages) Exar Corporation – SINGLE T1/E1/J1 FRAMER/LIU COMBO

XRT86L30
REV. 1.0.0
SINGLE T1/E1/J1 FRAMER/LIU COMBO
The Framer IC further supports the "Interrupt Block" Hierarchy by providing the "Block Interrupt Enable
Register. The bit-format of this register is identical to that for the "Block Interrupt Status Register", and is
presented below for the sake of completeness.
REGISTER 322
BIT
FUNCTION
7 SA6_ENB
6 LBCODE_ENB
5 RXCLKLOSS
4 ONESEC_ENB
3 HDLC_ENB
2 SLIP_ENB
1 ALARM_ENB
0 T1/E1FRAME_ENB
TABLE 167: BLOCK INTERRUPT ENABLE REGISTER
BLOCK INTERRUPT ENABLE REGISTER (BIER)
HEX ADDRESS: 0X0B01
TYPE DEFAULT
DESCRIPTION-OPERATION
R/W
0
SA6 interrupt enable
R/W
0
Loopback code interrupt enable
R/W
0
RxLineClk Loss Interrupt Enable
0 = Disables interrupt
1 = Enables interrupt
R/W
0
One Second Interrupt Enable
0 = Disables interrupt
1 = Enables Interrupt
R/W
0
HDLC Block Interrupt Enable
0 = Disables all HDLC Block interrupts
1 = Enables HDLC Block (for interrupt generation) at the block level
R/W
0
Slip Buffer Block Interrupt Enable
0 = Disables all Slip Buffer Block Interrupts
1 = Enables Slip Buffer Block at the block level
R/W
0
Alarm & Error Block Interrupt Enable
0 = Disables all Alarm & Error Block interrupts
1 = Enables Alarm & Error block at the block level
R/W
0
T1/E1 Frame Block Enable
0 = Disables all Frame Block interrupts
1 = Enables the Frame Block at the block level
The Block Interrupt Enable Register permits the user to individually enable or disable the interrupt requesting
capability of each of the "interrupt blocks" within the Framer. If a particular bit-field, within this register contains
the value "0"; then the corresponding functional block has been disabled from generating any interrupt
requests.
The procedures for configuring, enabling and servicing interrupts for each of these hierarchical levels is
discussed below.
3.6.1 Configuring the Interrupt System, at the Framer Level
The XRT86L30 Framer IC permits the user to enable or disable each of the four Framers for interrupt
generation. Further, the chip permits the user to make the following configuration selection.
1. Whether the "source-level" Interrupt Status bits are "Reset-upon-Read" or "Write-to-Clear".
2. Whether or not an "activated interrupt" is automatically cleared.
3.6.1.1 Enabling/Disabling the Framer for Interrupt Generation
Each of the four Framers of the XRT86L30 Framer can be enabled or disabled for interrupt generation. This
selection is made by writing the appropriate “0” or “1” to bit 0 (INTRUP_EN) of the "Interrupt Control Register"
corresponding to that framer, (see Table 168.)
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