XR16V2651 Datasheet, PDF (13/51 Pages) Exar Corporation – HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE

REV. P1.0.0
PRELIMINARY
XR16V2651
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE
TABLE 6: TYPICAL DATA RATES WITH A 24 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING
Required
Output Data
Rate
400
2400
4800
9600
10000
19200
25000
28800
38400
50000
57600
75000
100000
115200
153600
200000
225000
230400
250000
300000
400000
460800
500000
750000
921600
1000000
DIVISOR FOR
16x Clock
(Decimal)
3750
625
312.5
156.25
150
78.125
60
52.0833
39.0625
30
26.0417
20
15
13.0208
9.7656
7.5
6.6667
6.5104
6
5
3.75
3.2552
3
2
1.6276
1.5
DIVISOR
OBTAINABLE IN
V2651
DLM PROGRAM
VALUE (HEX)
DLL PROGRAM DLD PROGRAM
VALUE (HEX) VALUE (HEX)
DATA ERROR
RATE (%)
3750
E
A6
0
0
625
2
71
0
0
312 8/16
1
38
8
0
156 4/16
0
9C
4
0
150
0
96
0
0
78 2/16
0
4E
2
0
60
0
3C
0
0
52 1/16
0
34
1
0.04
39 1/16
0
27
1
0
30
0
1E
0
0
26 1/16
0
1A
1
0.08
20
0
14
0
0
15
0
F
0
0
13
0
D
0
0.16
9 12/16
0
9
C
0.16
7 8/16
0
7
8
0
6 11/16
0
6
B
0.31
6 8/16
0
6
8
0.16
6
0
6
0
0
5
0
5
0
0
3 12/16
0
3
C
0
3 4/16
0
3
4
0.16
3
0
3
0
0
2
0
2
0
0
1 10/16
0
1
A
0.16
1 8/16
0
1
8
0
2.10 Transmitter
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 32 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X/8X/4X
internal clock. A bit time is 16/8/4 clock periods (see DLD[5:4]). The transmitter sends the start-bit followed by
the number of data bits, inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO
and TSR are reported in the Line Status Register (LSR bit-5 and bit-6).
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