XR16V2651 Datasheet, PDF (10/51 Pages) Exar Corporation – HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE

XR16V2651
PRELIMINARY
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE
REV. P1.0.0
2.6 DMA Mode
The device does not support direct memory access. The DMA Mode (a legacy term) in this document doesn’t
mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of
the RXRDY# A/B and TXRDY# A/B output pins. The transmit and receive FIFO trigger levels provide additional
flexibility to the user for block mode operation. The LSR bits 5-6 provide an indication when the transmitter is
empty or has an empty location(s) for more data. The user can optionally operate the transmit and receive
FIFO in the DMA mode (FCR bit-3=1). When the transmit and receive FIFO are enabled and the DMA mode is
disabled (FCR bit-3 = 0), the V2651 is placed in single-character mode for data transmit or receive operation.
When DMA mode is enabled (FCR bit-3 = 1), the user takes advantage of block mode operation by loading or
unloading the FIFO in a block sequence determined by the selected trigger level. In this mode, the V2651 sets
the TXRDY# pin when the transmit FIFO becomes full, and sets the RXRDY# pin when the receive FIFO
becomes empty. The following table shows their behavior. Also see Figures 19 through 24.
TABLE 3: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE
PINS
FCR BIT-0=0
(FIFO DISABLED)
RXRDY# A/B LOW = 1 byte
HIGH = no data
FCR BIT-0=1 (FIFO ENABLED)
FCR Bit-3 = 0
(DMA Mode Disabled)
LOW = at least 1 byte in FIFO
HIGH = FIFO empty
FCR Bit-3 = 1
(DMA Mode Enabled)
HIGH to LOW transition when FIFO reaches the
trigger level, or time-out occurs
LOW to HIGH transition when FIFO empties
TXRDY# A/B LOW = THR empty LOW = FIFO empty
LOW = FIFO has at least 1 empty location
HIGH = byte in THR HIGH = at least 1 byte in FIFO HIGH = FIFO is full
2.7 INTA and INTB Outputs
The INTA and INTB interrupt output changes according to the operating mode and enhanced features setup.
Table 4 and 5 summarize the operating behavior for the transmitter and receiver. Also see Figures 19
through 24.
TABLE 4: INTA AND INTB PINS OPERATION FOR TRANSMITTER
FCR BIT-0 = 0
(FIFO DISABLED)
FCR BIT-0 = 1 (FIFO ENABLED)
INTA/B Pin
LOW = a byte in THR
HIGH = THR empty
LOW = FIFO above trigger level
HIGH = FIFO below trigger level or FIFO empty
INTA/B Pin
TABLE 5: INTA AND INTB PIN OPERATION FOR RECEIVER
FCR BIT-0 = 0
(FIFO DISABLED)
FCR BIT-0 = 1
(FIFO ENABLED)
LOW = no data
HIGH = 1 byte
LOW = FIFO below trigger level
HIGH = FIFO above trigger level
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