XRT75R12D_07 Datasheet, PDF (122/133 Pages) Exar Corporation – TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET

XRT75R12D
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.3
c. Configure each of the channels within the LIU to operate in the SONET De-Sync Mode
The user can accomplish this by executing of the following step.
• If the LIU has been configured to operate in the Host Mode
Then the user should clear Bit D2 (JA1) to "0" and set Bit D0 (JA0) to "1", within the Jitter Attenuator Control
Register, as depicted below.
TABLE 47: JITTER ATTENUATOR CONTROL REGISTER - CHANNEL N, ADDRESS LOCATION; 0XM7
(M = 0-5 & 8-D) (N = [0:11])
BIT 7
R/O
0
BIT 6
Unused
R/O
0
BIT 5
R/O
0
BIT 4
BIT 3
SONET APS
Recovery
Time
DisableCh_n
JA RESET
Ch_n
R/W
R/W
0
0
BIT 2
JA1 Ch_n
BIT 1
JA in Tx Path
Ch_n
BIT 0
JA0 Ch_n
R/W
R/W
R/W
0
0
1
Once the user accomplishes this step, then the Jitter Attenuator (within the LIU) will be configured to operate
with a very narrow bandwidth.
d. Configure the Jitter Attenuator (within each of the channels) to operate in the Transmit Direction.
The user can accomplish this by executing the following step.
• If the LIU has been configured to operate in the Host Mode.
Then the user should set Bit D1 (JATx/JARx*) to "1", within the Jitter Attenuator Control Register, as depicted
below.
TABLE 48: JITTER ATTENUATOR CONTROL REGISTER - CHANNEL N, ADDRESS LOCATION; 0XM7
(M = 0-5 & 8-D) (N = [0:11])
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
SONET APS
Recovery
Time
DisableCh_n
JA RESET
Ch_n
JA1 Ch_n JA in Tx Path JA0 Ch_n
Ch_n
R/O
R/O
R/O
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
1
1
e. Enable the "SONET APS Recovery Time" Mode
Finally, if the user intends to use the LIU in an Application that is required to reacquire proper SONET and DS3
traffic, prior within 50ms of an APS (Automatic Protection Switching) event (per Telcordia GR-253-CORE), then
the user should clear Bit 4 (SONET APS Recovery Time Disable), within the "Jitter Attenuator Control"
Register, to "0" as depicted below.
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