XR18W750 Datasheet, PDF (10/44 Pages) Exar Corporation – WIRELESS UART CONTROLLER

XR18W750
WIRELESS UART CONTROLLER
REV. 1.0.0
3.2 Parallel Mode (CPU) Interface
In the parallel mode, the CPU interface is 8 data bits wide with 3 address lines and control signals to execute
data bus read and write transactions. The XR18W750 data interface supports both the Intel and Motorola
compatible types of CPUs and is compatible to the industry standard 16C550 UART. Each bus cycle is
asynchronous using CS#, IOR# and IOW#, or CS# and R/W# inputs. A typical data bus interconnection for
Intel and Motorola mode is shown in Figure 4.
FIGURE 4. XR18W750 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS (PARALLEL MODE)
A2:A0
D7:D0
UART_CS#
IOW#
IOR#
RESET
UART_INT
TXRDY#
RXRDY#
VCC
GND
A2:A0
D7:D0
UART_CS#
R/W#
VCC
RESET#
VCC
UART_IRQ#
TXRDY#
RXRDY#
GND
GND
A2:A0
D7:D0
CS#
IOW#
IOR#
RESET
INT
TXRDY#
RXRDY#
16/68#
UART
S/P#
TX
RX
RTS#
CTS#
A2:A0
D7:D0
CS#
IOW#
IOR#
INT
8051
Microprocessor
RX
TX
CTS#
RTS#
UART
Intel Data Bus Interconnections
A2:A0
D7:D0
CS#
IOW#
IOR#
RESET
INT
TXRDY#
RXRDY#
16/68#
UART
S/P#
TX
RX
RTS#
CTS#
A2:A0
D7:D0
CS#
IOW#
IOR#
INT
8051
Microprocessor
RX
TX
CTS#
RTS#
UART
Motorola Data Bus Interconnections
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