XRK79892 Datasheet, PDF (1/10 Pages) Exar Corporation – INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER

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PRELIMINARY
XRK79892
INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER
JANAUARY 2005
GENERAL DESCRIPTION
The XRK79892 is a PLL clock driver designed
specifically for redundant clock tree designs. The
device receives two differential LVPECL clock signals
from which it generates 5 new differential LVPECL
clock outputs. Two of the output pairs regenerate the
input signals frequency and phase while the other
three pairs generate 4x, phase aligned clock outputs.
External PLL feedback is used to also provide zero
delay buffer performance.
REV. P1.0.1
phase/frequency alignment will occur with minimal
output phase disturbance. The typical phase bump
caused by a failed clock is eliminated.
FEATURES
• Fully Integrated PLL
• Intelligent Dynamic Clock Switch
• LVPECL Clock Outputs
• LVCMOS Control I/O
The XRK79892 Intelligent Dynamic Clock Switch
circuit continuously monitors both input CLK signals.
Upon detection of a failure (CLK stuck HIGH or LOW
for at least 1 period), the INP_BAD for that CLK will
be latched (H). If that CLK is the primary clock, the
device will switch to the good secondary clock and
• 3.3V Operation
• 32-Lead LQFP Packagin
• Pin compatible with MPC9892i
FIGURE 1. BLOCK DIAGRAM OF THE XRK79892
CLK_Selected
INP1Bad
INP0Bad
Man_Override
Alarm_Reset
Sel_CLK
CLK0
CLK0
CLK1
CLK1
Ext_FB
Ext_FB
MR
Dynamic
Switch
Logic
OR
÷4
PLL
÷16
800-1600MHz
PLL_En
Qb0
Qb0
Qb1
Qb1
Qb2
Qb2
Qa0
Qa0
Qa1
Qa1
PRODUCT ORDERING INFORMATION
PRODUCT NUMBER
XRK79892IQ
PACKAGE TYPE
32-Lead LQFP
OPERATING TEMPERATURE RANGE
-40°C to +85°C
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • [phone] • FAX [phone] • www.exar.com