XR28V382 Datasheet, PDF (1/39 Pages) Exar Corporation – 3.3V DUAL LPC UART WITH 128-BYTE FIFO

XR28V382
3.3V DUAL LPC UART WITH 128-BYTE FIFO
DECEMBER 2013
REV. 1.0.1
GENERAL DESCRIPTION
The XR28V382 (V382) is a dual Universal
Asynchronous Receiver and Transmitter (UART) for
the Intel Low Pin Count (LPC) bus interface. This
device can replace or supplement a Super I/O device
to add additinal serial ports to the system.
The V382 UARTs support any 16-bit I/O address
supported by the system. The register set is based on
the industry standard 16550 UART, so the V382
operates with standard serial port drivers without
requiring a custom driver to be installed.
The 128 byte Transmit and Receive FIFOs reduce
CPU overhead and minimize the chance of buffer
overflow and data loss. In addition to the 16550 UART
registers, there are also Configuration register set
where enhanced features such as the 9-bit (multidrop)
mode, IrDA mode and the Watchdog Timer can be
enabled.
The V382 is available in a 32-pin QFN package.
APPLICATIONS
x Industrial and Embedded PCs
x Factory Automation and Process Controls
x Network Routers
x System Board Designs
FEATURES
x 128 Byte Transmit and Receive FIFO
x Compliant to LPC 1.1 Specifications
x -40°C to +85°C Industrial Temp Operation
x Watchdog Timer with WDTOUT# signal
x 2 independent UART channels
■ Programmable I/O mapped base addresses
■ Data rates up to 3 Mbps
■ Selectable RX FIFO interrupt trigger levels
■ Auto RS-485 Half-Duplex Control mode
■ Programmable character lengths (5, 6, 7, 8)
with even, odd, or no parity
■ IrDA mode and separate IRTXA# and IRRXA#
pins for the first UART channel
■ 9-bit (Multidrop) mode
x External 24MHz/48MHz clock
x Single 3.3V Supply Voltage ( ± 10%)
x 5V tolerant inputs
x 32-QFN package (5mm x 5mm)
FIGURE 1. XR28V382 BLOCK DIAGRAM
VCC
GND
P C IR S T #
LCLK
LFRAME#
L A D [3 :0 ]
SER IR Q
3.3V ± 10%
LPC
Bus
Interface
G lobal
C o n fig u ra tio n
R e g is te rs
Baud
R a te
G e n e ra to r
TX FIFO
(IrDA Encoder)
RX FIFO
(IrDA Decoder)
Status and
C o n tro l
R egisters
M odem IOs
UART Channel A
TXA / PS_3F8_IRQA
IR TXA# / PS_CO NF_KEY0
RXA
IR RXA#
R TSA#/PS_C O NF_2E/R S485
D TR A#/PS_3E0_IR Q A
CTSA#, DSRA#, CDA#, RIA#
W D TO U T#/
PS_W D T
C L K IN
W atch
Dog
Tim er
C lock
D iv id e r
Baud
R a te
G enerator
TX FIFO
RX FIFO
Status and
C o n tro l
R e g iste rs
M odem IOs
UART Channel B
TXB / PS_2F8_IR Q B
RXB
R T S B # /P S _ C O N F _ K E Y 1 /R S 4 8 5
D T R B # /P S _ 2 E 0 _ IR Q B
CTSB#, DSRB#, CDB#,
R IB #
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