XR16V2551 Datasheet, PDF (1/51 Pages) Exar Corporation – HIGH PERFORMANCE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE

PRELIMINARY
XR16V2551
JUNE 2006
HIGH PERFORMANCE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE
REV. P1.0.0
GENERAL DESCRIPTION
The XR16V2551¹ (V2551) is a high performance dual
universal asynchronous receiver and transmitter
(UART) with 16 byte TX and RX FIFOs. The device
operates from 2.25 to 3.6 volts with 5 Volt tolerant
inputs and is pin-to-pin compatible to Exar’s
XR16V2651 and XR16L2551. The device includes 2
additional capabilities over the XR16V2550: Intel and
Motorola data bus selection and a “PowerSave”
mode to further reduce sleep current to a minimum
during sleep mode. It supports Exar’s enhanced
features of selectable FIFO trigger level, automatic
hardware (RTS/CTS) and software flow control, and a
complete modem interface. An internal loopback
capability allows system diagnostics. Independent
programmable fractional baud rate generators are
provided in each channel to select data rates up to 16
Mbps at 3.3 Volt and 4X sampling clock. The V2551
is available in 48-pin TQFP and 32-pin QFN
packages.
NOTE: 1 Covered by U.S. Patent #5,649,122
APPLICATIONS
• Portable Appliances
• Telecommunication Network Routers
• Ethernet Network Routers
• Cellular Data Devices
• Factory Automation and Process Controls
FEATURES
• 2.25 to 3.6 Volt Operation
• 5 Volt Tolerant Inputs
• Pin-to-pin compatible to Exar’s XR16V2651 and the
XR16L2551
• Two independent UART channels
■ Register set identical to 16V2550
■ Data rate of up to 16 Mbps at 3.3 V, and 12.5
Mbps at 2.5 V with 4X sampling rate
■ Fractional Baud Rate Generator
■ Transmit and Receive FIFOs of 16 bytes
■ Selectable TX and RX FIFO Trigger Levels
■ Automatic Hardware (RTS/CTS) Flow Control
■ Automatic Software (Xon/Xoff) Flow Control
■ Wireless Infrared (IrDA 1.0) Encoder/Decoder
■ Automatic sleep mode with wake-up interrupt
■ Full modem interface
• PowerSave Feature reduces sleep current to 15 µA
• Device Identification and Revision
• Crystal oscillator (up to 32MHz) or external clock
(up to 64MHz) input
• 48-TQFP and 32-QFN packages
FIGURE 1. XR16V2551 BLOCK DIAGRAM
PwrSave
A2:A0
D7:D0
IOR# (VCC)
IOW# (R/W#)
CSA# (CS#)
CSB# (A3)
INTA (IRQ#)
INTB (logic 0)
TXRDYA#
TXRDYB#
RXRDYA#
RXRDYB#
Reset (Reset#)
16/68#
CLKSEL
Intel or
Motorola
Data Bus
Interface
*5 Volt Tolerant Inputs
UART Channel A
UART
Regs
BRG
16 Byte TX FIFO
TX & RX
IR
ENDEC
16 Byte RX FIFO
UART Channel B
(same as Channel A)
Crystal Osc/Buffer
2.25 to 3.6V VCC
GND
TXA, RXA, DTRA#,
DSRA#, RTSA#,
DTSA#, CDA#, RIA#,
OP2A#
TXB, RXB, DTRB#,
DSRB#, RTSB#,
CTSB#, CDB#, RIB#,
OP2B#
XTAL1
XTAL2
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • [phone] • FAX [phone] • www.exar.com