DAN-140 Datasheet, PDF (1/3 Pages) Exar Corporation – EXAR’S XR16C850 COMPARED

DATA COMMUNICATIONS APPLICATION NOTE
DAN140
August 2002
EXAR’S XR16C850 COMPARED WITH OXFORD’S OX16C950
Author: PY
1.0 INTRODUCTION
This application note describes the major difference between Exar’s XR16C850 with Oxford’s OX16C950.
These devices are very similar, with a few hardware, firmware-related and bus timing differences.
1.1 HARDWARE DIFFERENCES
• The Oxford OX16C950 and Exar XR16C850 are available in the 48-pin TQFP and 44-pin PLCC packages.
Additionally, the XR16C850 is available in the 40-pin PDIP (for compatibility to early families) and 52-pin
QFP packages.
• In the 48-pin TQFP package, the Exar and Oxford UARTs are pin-to-pin compatible if pin 36 is tied to VCC.
• In the 44-pin PLCC package, the Exar and Oxford UARTs are pin-to-pin compatible if pin 34 is tied to VCC.
• Here is a summary of the pin differences between the XR16C850 and OX16C950 and the changes that need
to be made when replacing the OX16C950 with the XR16C850:
TABLE 1: PIN DIFFERENCES BETWEEN THE XR16C850 AND OX16C950
OX16C950
PIN NAME
XR16C850
PIN NAME
44-PLCC 48-TQFP
PIN
PIN
NUMBER NUMBER
CHANGES/COMMENTS
N.C.
CLKSEL
N/A
CLKSEL
N.C.
23
N.C.
BUS8/16
N/A
INTSEL#
SEL
34
FIFOSEL
N.C.
1
VSEL
N.C.
N/A
13 No change necessary. CLKSEL pin on XR16C850 has internal pull-up.
21 No change necessary. CLKSEL function can be performed via internal
register MCR bit-7 in the XR16C850.
25 No change necessary. BUS8/16 pin on XR16C850 has internal pull-up.
36
Only pin-to-pin compatible if this pin is connected to VCC.
If this pin is tied to GND, XR16C850 will be in PC Mode.
37 No change necessary. OX16C950 selects FIFO depths of 16 or 128 byte
FIFOs. XR16C850 FIFO depth is always 128 bytes.
48 No change necessary. XR16C850 can operate at 5 or 3.3 V in all pack-
ages. VSEL pin on OX16C950 selects between 5 and 3 V operation.
OX16C950 in 44-pin PLCC package can only operate at 5 V.
• The XR16C850 can operate in both the Intel and PC Mode while the OX16C950 can only operate in the Intel
Bus Mode.
1.2 BUS TIMING DIFFERENCES
• The OX16C950 requires that the -CS pin is asserted before the -IOR or -IOW pin at the beginning of the
read/write cycle and the -IOR or -IOW pin must be de-asserted before the -CS pin is de-asserted at the end
of the cycle. During a read, the Exar UART can have either the -CS or the -IOR signal asserted first and
have either signal be de-asserted first. The signals are wire-ORed in the Exar UART, therefore the second
signal asserted initiates the read cycle and the first signal de-asserted terminates the read cycle. The same
is true during a write for -CS and -IOW. The flexibility of the Exar UARTs timing can be important in designs
using DSP, ARM, and MIPS processors.
EXAR Corporation 48720 Kato Road, Fremont CA, 94538 • [phone] • FAX [phone] • www.exar.com • [e-mail]