EM68C08CWAE-18H Datasheet, PDF (59/63 Pages) Etron Technology, Inc. – 128M x 8 bit DDRII Synchronous DRAM (SDRAM)

EtronTech
EM68C08CWAE
Figure 52. Read with autoprecharge to power-down entry
T0
T1
T2
CK#
CK
Tx
Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8 Tx+9
CMD
CKE
DQ
DQS
DQS#
RDA
BL=4
PRE
AL+BL/2 with tRTP = 7.5ns
& tRAS min satisfied
AL+CL
QQQQ
CKE should be kept HIGH until the end of burst operation
t_IS
T0
CK#
CK
CMD
CKE
DQ
DQS
DQS#
T1
T2
Tx
Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8 Tx+9
RD
BL=8
AL+BL/2 with tRTP = 7.5ns
& tRAS min satisfied
PRE
Start internal precharge
CKE should be kept HIGH until the end of burst operation
AL+CL
QQQQQQQQ
t_IS
Figure 53. Write to power-down entry
T0
T1
Tm
Tm+1 Tm+2 Tm+3
Tx
Tx+1 Tx+2
Ty
Ty+1 Ty+2 Ty+3
CK#
CK
CMD
CKE
DQ
DQS
DQS#
WR
BL=4
WL
QQQQ
t_IS
tWTR
T0
CK#
CK
CMD
CKE
DQ
DQS
DQS#
T1
Tm
Tm+1 Tm+2 Tm+3 Tm+4 Tm+5
Tx
Tx+1 Tx+2 Tx+3 Tx+4
WR
BL=8
WL
QQQQQQQQ
t_IS
tWTR
Rev. 1.3
59
Oct. /2015