EM68C08CWAE-18H Datasheet, PDF (16/63 Pages) Etron Technology, Inc. – 128M x 8 bit DDRII Synchronous DRAM (SDRAM)

EtronTech
EM68C08CWAE
z Bank activate command
The Bank Activate command is issued by holding CAS# and WE# HIGH with CS# and RAS# LOW at the rising
edge of the clock. The bank addresses BA0-BA2 are used to select the desired bank. The row addresses A0
through A13 are used to determine which row to activate in the selected bank. The Bank Activate command must
be applied before any Read or Write operation can be executed. Immediately after the bank active command, the
DDR2 SDRAM can accept a read or write command (with or without Auto-Precharge) on the following clock cycle.
If a R/W command is issued to a bank that has not satisfied the t_RCDmin specification, then additive latency must be
programmed into the device to delay the R/W command which is internally issued to the device. The additive
latency value must be chosen to assure t_RCDmin is satisfied. Additive latencies of 0, 1, 2, 3, and 4 are supported.
Once a bank has been activated it must be precharged before another Bank Activate command can be applied to
the same bank. The bank active and precharge times are defined as t_RAS and t_RP, respectively. The minimum time
interval between successive Bank Activate commands to the same bank is determined (t_RC). The minimum time
interval between Bank Active commands is t_RRD
In order to ensure that 8 bank devices do not exceed the instantaneous current supplying capability of 4 bank
devices, certain restrictions on operation of the 8 bank devices must be observed. There are two rules. One for
restricting the number of sequential ACT commands that can be issued and another for allowing more time for
RAS precharge for a Precharge All command. The rules are as follows:
- 8 bank device Sequential Bank Activation Restriction: No more than 4 banks may be activated in a rolling t_FAW
window. Converting to clocks is done by dividing t_FAW[ns] by t_CK[ns] or t_CK[ns], depending on the speed bin, and
rounding up to next integer value. As an example of the rolling window, if RU {(t_FAW / t_CK)} or RU {(t_FAW / t_CK)} is 10
clocks, and an activate command is issued in clock N, no more than three further activate commands may be
issued at or between clock N+1 and N+9.
- 8 bank device Precharge All Allowance : t_RP for a Precharge All command for an 8 Bank device will equal to t_RP +
1 x t_CK or t_RP + 1 x t_CK, depending on the speed bin, where t_RP = RU{ t_RP / t_CK} and t_RP is the value for a single bank
precharge.
z Read and Write access modes
After a bank has been activated, a Read or Write cycle can be executed. This is accomplished by setting RAS#
HIGH, CS# and CAS# LOW at the clock’s rising edge. WE# must also be defined at this time to determine whether
the access cycle is a Read operation (WE# HIGH) or a Write operation (WE# LOW). The DDR2 SDRAM provides
a fast column access operation. A single Read or Write Command will initiate a serial Read or Write operation on
successive clock cycles. The boundary of the burst cycle is strictly restricted to specific segments of the page
length. Any system or application incorporating random access memory products should be properly designed,
tested, and qualified to ensure proper use or access of such memory products. Disproportionate, excessive, and/or
repeated access to a particular address or addresses may result in reduction of product life.
z Posted CAS#
Posted CAS# operation is supported to make command and data bus efficient for sustainable bandwidths in DDR2
SDRAM. In this operation, the DDR2 SDRAM allows a CAS# Read or Write command to be issued immediately
after the RAS bank activate command (or any time during the RAS# -CAS#-delay time, t_RCD, period). The
command is held for the time of the Additive Latency (AL) before it is issued inside the device. The Read Latency
(RL) is controlled by the sum of AL and the CAS latency (CL). Therefore if a user chooses to issue a R/W
command before the t_RCDmin, then AL (greater than 0) must be written into the EMR(1). The Write Latency (WL) is
always defined as RL - 1 (Read Latency -1) where Read Latency is defined as the sum of additive latency plus
CAS latency (RL=AL+CL). Read or Write operations using AL allow seamless bursts (refer to seamless operation
timing diagram examples in Read burst and Write burst section)
z Burst Mode Operation
Burst mode operation is used to provide a constant flow of data to memory locations (Write cycle), or from memory
locations (Read cycle). The parameters that define how the burst mode will operate are burst sequence and burst
length. The DDR2 SDRAM supports 4 bit and 8 bit burst modes only. For 8 bit burst mode, full interleave address
ordering is supported, however, sequential address ordering is nibble based for ease of implementation. The burst
length is programmable and defined by the addresses A0 ~ A2 of the MRS. The burst type, either sequential or
interleaved, is programmable and defined by the address bit 3 (A3) of the MRS. Seamless burst Read or Write
operations are supported. Interruption of a burst Read or Write operation is prohibited, when burst length = 4 is
programmed. For burst interruption of a Read or Write burst when burst length = 8 is used, see the “Burst
Interruption“ section of this datasheet. A Burst Stop command is not supported on DDR2 SDRAM devices.
Rev. 1.3
16
Oct. /2015