EM68C08CWAG-18H Datasheet, PDF(57/63 Page) Etron Technology, Inc. – 128M x 8 bit DDRII Synchronous DRAM (SDRAM)

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EM68C08CWAG-18H Datasheet, PDF (57/63 Pages) Etron Technology, Inc. – 128M x 8 bit DDRII Synchronous DRAM (SDRAM)

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EtronTech

EM68C08CWAG

Figure 47. Self refresh operation

CK#

tCK

tCH tCL

CKE

ODT

VIL(ac)

tIS

CMD

tRP*

tAOFD

VIL(ac)

tIS

tIS tIH tIH

VIH(ac) Self VIH(dc)

VIL(ac) Refresh VIL(dc)

VIH(ac)

tIS

>=tXSNR

>=tXSRD

tIS

NOP

tIH

Valid

NOTE 1 Device must be in the "All banks idle" state prior to entering Self Refresh mode.

NOTE 2 ODT must be turned off tAOFD before entering Self Refresh mode, and can be

turned on again when tXSRD timing is satisfied.

NOTE 3 tXSRD is applied for Read or a Read with autoprecharge command.

tXSNR is applied for any command except a Read or a Read with autoprecharge command.

Figure 48. Basic power down entry and exit timing diagram

CK#

CKE

tIH

tIS

tIH

tIS

tIH

tIS tIH

Command

VALID

NOP

tCKE min

Enter Power-Down mode

NOP

VALID

tXARDS

Exit Power-Down mode

tXP, tXARD

tCKE(min)

VALID

or NOP

Don't Care

Figure 49. CKE intensive environment

CK#

tCKE

CKE

tCKE

NOTE: DRAM guarantees all AC and DC timing & voltage specifications and proper DLL operation with intensive CKE operation

tCKE

Rev. 1.1

Apr. /2016

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