EM68C08CWAG-18H Datasheet, PDF (53/63 Pages) Etron Technology, Inc. – 128M x 8 bit DDRII Synchronous DRAM (SDRAM)

EtronTech
EM68C08CWAG
Figure 39. Burst write followed by precharge: WL= (RL-1) =4
T0
T1
T2
T3
T4
T5
T6
T7
T9
CK#
CK
CMD
Post CAS#
Write A
NOP
DQS
DQS#
WL= 4
DQ's
NOP
NOP
NOP
NOP
NOP
NOP
Completion of the Burst Write
>=t_WR
Precharge A
DNA₀ DNA₁ DNA₂ DNA₃
Figure 40. Burst read operation with auto precharge:
(RL=4,AL=1, CL=3, BL=8, t_RTP≦2 clocks)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK#
CK
CMD
DQS
DQS#
DQ's
Post CAS#
READ A
Autoprecharge
AL = 1
NOP
NOP
NOP
AL + BL/2 clks
NOP
NOP
NOP
>= t_RP
NOP
Bank A
Activate
CL = 3
RL= 4
>=t_RTP
t_RTP
DOUT
A0
DOUT
A1
DOUT
A2
DOUT
A3
DOUT
A4
DOUT
A5
DOUT
A6
DOUT
A7
First 4-bit prefetch Second 4-bit prefetch Precharge begins here
Rev. 1.1
53
Apr. /2016