EM68B16CWPA Datasheet, PDF (41/59 Pages) Etron Technology, Inc. – 32M x 16 bit DDRII Synchronous DRAM (SDRAM)

EtronTech
EM68B16CWPA
Figure 21. Burst read followed by burst write: RL=5, WL= (RL-1) =4, BL=4
T0
CK#
CK
CMD Post CAS#
READ A
DQS
DQS#
T1
NOP
DQs
Tn-1
Tn
Tn+1
Tn+2
Tn+3
Tn+4
Tn+5
NOP
Post CAS#
WRITE A
NOP
t_RTW (Read to Write turn around time)
NOP
NOP
RL=5
WL = RL-1 = 4
Dout A0 Dout A1 Dout A2 Dout A3
NOP
NOP
Din A0 Din A1 Din A2 Din A3
NOTE : The minimum time from the burst read command to the burst write command is defined by a read-to-write-
turn-around-time, which is 4 clocks in case of BL = 4 operation, 6 clocks in case of BL = 8 operation.
Figure 22. Seamless burst read operation: RL=5, AL=2, CL=3, BL=4
T0
T1
CK#
CK
CMD Post CAS#
READ A
NOP
DQS
DQS#
AL=2
DQs
T2
T3
T4
Post CAS#
READ B
NOP
NOP
CL=3
RL=5
T5
T6
T7
T8
NOP
NOP
NOP
NOP
Dout A0 Dout A1 Dout A2 Dout A3 Dout B0 Dout B1 Dout B2
NOTE : The seamless burst read operation is supported by enabling a read command at every other clock for BL =
4 operation, and every 4 clock for BL =8 operation. This operation is allowed regardless of same or different banks
as long as the banks are activated.
Etron Confidential
41
Rev. 1.4
Mar. 2009