EM639325TS-5IG Datasheet, PDF (41/47 Pages) Etron Technology, Inc. – 4M x 32 bit Synchronous DRAM (SDRAM)

EtronTech
EM639325
Figure 39. Byte Read and Write Operation (Burst Length=4, CAS# Latency=3)
CLK
CKE
CS#
RAS#
CAS#
WE#
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
High
BA0, 1
A10
RAx
A0-A9,
RAx
CAx
A11
DQM m
CAy
CAz
DQM n
DQ M
Ax0 Ax1 Ax2
DAy1 Day2
Az1 Az2
DQ N
Ax1 Ax2 Ax3
DAy0 DAy1
DAy3
Az0 Az1 Az2 Az3
Activate
Command
Bank A
Read
Command
Bank A
Upper Byte Lower Byte
is masked is masked
Write
Command
Bank A
Upper Byte
is masked
Read
Command
Bank A
Lower Byte
is masked
Note : M represent DQ in the byte m; N represent DQ in the byte n.
Lower Byte
is masked
Don’t Care
Rev. 2.1
41
Aug. /2015