EM638165TS-5G Datasheet, PDF (38/53 Pages) Etron Technology, Inc. – 4M x 16 bit Synchronous DRAM (SDRAM)

EtronTech
EM638165
Figure 33.1. Interleaving Column Read Cycle (Burst Length=4, CAS# Latency=2)
CLK
CKE
CS#
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
RAS#
CAS#
WE#
BA0,1
A10
A0-A9,
A11
DQM
RAx
RAx
tRCD
DQ ^Hi-Z
Activate
Command
Bank A
CAy
RBx
RBx
CBw
CBx
CBy
CAy
CBz
tAC
Ax0 Ax1 Ax2 Ax3
Bw0 Bw1 Bx0 Bx1 By0 By1 Ay0 Ay1 Bz0 Bz1 Bz2 Bz3
Read
Command
Bank A
Activate
Command
Bank B
Read
Command
Bank B
Read
Command
Bank B
Read
Command
Bank B
Read
Command
Bank A
Read
Command
Bank B
Precharge
Command
Bank A
Precharge
Command
Bank B
Don’t Care
Rev. 5.3
38
Dec. /2013