EM6AA160TSA Datasheet, PDF (3/54 Pages) Etron Technology, Inc. – 16M x 16 bit DDR Synchronous DRAM (SDRAM)

EtronTech
EM6AA160TSA
Pin Descriptions
Table 2. Pin Details of EM6AA160
Symbol Type
Description
CK, _CK
Input
Differential Clock: CK, _CK are driven by the system clock. All SDRAM input signals
are sampled on the positive edge of CK. Both CK and _CK increment the internal
burst counter and controls the output registers.
CKE
Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal. If CKE
goes low synchronously with clock, the internal clock is suspended from the next
clock cycle and the state of output and burst address is frozen as long as the CKE
remains low. When all banks are in the idle state, deactivating the clock controls the
entry to the Power Down and Self Refresh modes.
BA0, BA1
Input Bank Activate: BA0 and BA1 define to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied.
A0-A12
Input Address Inputs: A0-A12 are sampled during the BankActivate command (row
address A0-A12) and Read/Write command (column address A0-A8 with A10 defining
Auto Precharge).
CS
Input Chip Select: _CS enables (sampled LOW) and disables (sampled HIGH) the
command decoder. All commands are masked when _CS is sampled HIGH. _CS
provides for external bank selection on systems with multiple banks. It is considered
part of the command code.
RAS
Input
Row Address Strobe: The _RAS signal defines the operation commands in
conjunction with the _CAS and _WE signals and is latched at the positive edges of
CK. When _RAS and _CS are asserted "LOW" and _CAS is asserted "HIGH," either
the BankActivate command or the Precharge command is selected by the _WE
signal. When the _WE is asserted "HIGH," the BankActivate command is selected
and the bank designated by BA is turned on to the active state. When the _WE is
asserted "LOW," the Precharge command is selected and the bank designated by BA
is switched to the idle state after the precharge operation.
CAS
Input
Column Address Strobe: The _CAS signal defines the operation commands in
conjunction with the _RAS and _WE signals and is latched at the positive edges of
CK. When _RAS is held "HIGH" and _CS is asserted "LOW," the column access is
started by asserting _CAS "LOW." Then, the Read or Write command is selected by
asserting _WE "HIGH" or “LOW”.
WE
Input _{Write Enable: The WE signal defines the operation commands in conjunction with}
the _RAS and _CAS signals and is latched at the positive edges of CK. The _WE input
is used to select the BankActivate or Precharge command and Read or Write
command.
LDQS,
UDQS
Input / Bidirectional Data Strobe: Specifies timing for Input and Output data. Read Data
Output
Strobe is edge triggered. Write Data Strobe provides a setup and hold time for data
and DQM. LDQS is for DQ0~7, UDQS is for DQ8~15.
LDM,
UDM
Input Data Input Mask: Input data is masked when DM is sampled HIGH during a write
cycle. LDM masks DQ0-DQ7, UDM masks DQ8-DQ15.
DQ0 - DQ15 Input / Data I/O: The DQ0-DQ15 input and output data are synchronized with the positive
Output edges of CK and _CK The I/Os are byte-maskable during Writes.
Etron Confidential
3
Rev. 1.2
May 2009