EM6A9325 Datasheet, PDF (26/51 Pages) Etron Technology, Inc. – 4M x 32 Low Power SDRAM (LPSDRAM)

EtronTech _{4M x 32 LPSDRAM}
Figure 6.3. Clock Suspension During Burst Read (Using CKE)
(Burst Length=4, CAS# Latency=3)
EM6A9325
CLK
CKE
T0 T 1 T 2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK3
CS#
RAS#
CAS#
WE #
BS0,1
A10
A0-A9
DQM
RAx
RAx
CAx
DQ Hi-Z
Ax0
Ax1
Ax2
Activate
Command
Bank A
Read
Command
Bank A
Clock Suspend Clock Suspend
1 Cycle
2 Cycles
Note: CKE to CLK disable/enable = 1 clock
tHZ
Ax3
Clock Suspend
3 Cycles
Preliminary
26
Rev 0.4
June 2003