NUC960ADN Datasheet, PDF (99/420 Pages) Nuvoton Technology Corporation – 32-BIT ARM926EJ-S BASED MCU

NUC960ADN
31
30
Owner
23
22
Reserved
RP
15
14
7
6
Bits
Descriptions
[31:30] Owner
[29:23] Rx Status
[22]
RP
29
21
ALIE
13
5
32-BIT ARM926EJ-S BASED MCU
28
27
26
Reserved
20
19
18
RXGD
PTLE
Reserved
12
11
10
RBC
4
3
2
RBC
25
17
CRCE
9
1
24
16
RXINTR
8
0
Ownership
The ownership field defines which one, the CPU or EMC, is the owner of
each Rx descriptor. Only the owner has right to modify the Rx descriptor
and the others can read the Rx descriptor only.
00: The owner is CPU
01: Undefined
10: The owner is EMC
11: Undefined
If the O=2’b10 indicates the EMC RxDMA is the owner of Rx descriptor
and the Rx descriptor is available for frame reception. After the frame
reception completed, if the frame needed NAT translation, EMC RxDMA
modify ownership field to 2’b11. Otherwise, the ownership field will be
modified to 2’b00.
If the O=2’b00 indicates the CPU is the owner of Rx descriptor. After the
CPU completes processing the frame, it modifies the ownership field to
2’b10 and releases the Rx descriptor to EMC RxDMA.
Receive Status
This field keeps the status for frame reception. All status bits are
updated by EMC. In the receive status, bits 29 to 23 are undefined and
reserved for the future.
Runt Packet
The RP indicates the frame stored in the data buffer pointed by Rx
descriptor is a short frame (frame length is less than 64 bytes).
1’b0: The frame is not a short frame.
1’b1: The frame is a short frame.
99
Publication Release Date: Jun. 18, 2010
Revision: A3