SGP02G72A1BQ1SA-DCRT Datasheet, PDF (9/17 Pages) List of Unclassifed Manufacturers – 2048MB DDR3 –Registered ECC RDIMM

Preliminary Data Sheet
Rev.0.9 16.01.2014
DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS
(0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.5V ± 0.075V, VDD = +1.5V ± 0.075V)
AC CHARACTERISTICS
12800 CL11
PARAMETER
SYMBOL MIN MAX
Clock cycle time CL = 11
CL = 10
CL = 9
CL = 8
CL = 7
CL = 6
CL = 5
Read CMD to 1^st data
CK high-level width
CK low-level width
t_CK (11)
t_CK (10)
t_CK (9)
t_CK (8)
t_CK (7)
t_CK (6)
t_CK (5)
t_AA
t_CH (avg)
t_CL (avg)
1.25
1.5
1.5
1.875
1.875
2.5
3.0
13.75
0.47
0.47
1.5
<1.875
<1.875
<2.5
<2.5
3.3
3.3
-
0.53
0.53
Data-out high-impedance
t_HZ
window from CK/CK#
-
225
Data-out low-impedance window t_LZ
from CK/CK#
-450 225
DQ and DM input pulse width
( for each input )
t_DIPW
360
-
DQ-DQS hold, DQS to first DQ t_QH
to go non-valid, per access
0.38
-
DQS input high pulse width
t_DQSH
0.45 0.55
DQS input low pulse width
t_DQSL
0.45 0.55
DQS read preamble
t_RPRE
0.9
Note¹
DQS read postamble
t_RPST
0.3
Note²
DQS write preamble
t_WPRE
0.9
-
DQS write postamble
t_WPST
0.3
-
1 _{The maximum preamble is bound by tLZDQS (MAX)}
2 _{The maximum postamble is bound by tHZDQS (MAX)}
10600 CL9
MIN
MAX
-
-
1.5 <1.875
1.5 <1.875
1.875 <2.5
1.875 <2.5
2.5
3.3
3.0
3.3
13.5
-
0.47
0.53
0.47
0.53
-
250
-500
250
400
-
0.38
0.45
0.45
0.9
0.3
0.9
0.3
-
0.55
0.55
Note¹
Note²
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
ns
ns
tCK
(AVG)
tCK
tCK
tCK
tCK
tCK
tCK
The DQ, DQS setup and hold times as well as Command/Address setup and hold times need to be calculated using the
respective component data sheets with derating tables and the driver slew rate in combination with the JEDEC min/max
routing information
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: [phone]
Fax: [phone]
www.swissbit.com
eMail: [e-mail]
Page 9
of 17