SBN0064G Datasheet, PDF (9/37 Pages) List of Unclassifed Manufacturers – Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory

Avant Electronics
SBN0064G
Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory
Pad
number
SYMBOL
I/O
DESCRIPTION
External LCD Bias voltage.
74, 75, V3L, V2L,
76, 77 V5L, V0L
Input
Note that V0L, V2L, V3L, and V5L must be connected to external bias voltages
V_DD, V2, V3, and V5, respectively, and the condition VDD≥V1≥V2≥V3≥V4≥V5 must
always be met.
78
79~86
87, 88,
89
90
V_SS
DB0~DB7 I/O
CS3, CS2B,
CS1B
Input
RSTB
Input
In addition, V_LCD (V_DD - V5) should not exceed 13 volts.
Ground.
Bi-direction, tri-state 8-bit parallel data bus for interface with a host microcontroller.
This data bus is for data transfer between the host microcontroller and the
SBN0064G.
Chip Selection
To enable selecting the SBN0064G as a peripheral device of the microcontroller,
the condition CS3=1, CS2B=0, and CS1B=0 must be met.
Hardware reset input.
A LOW pulse added to this input resets the internal circuit of the SBN0064G. The
duration of the low pulse must be longer than 1 µS.
Read/Write (R/W) control signal from the host microcontroller.
91
R/W
Input
This pin should be connected to the R/W output of the host microcontroller. A HIGH
level on this pin indicates that the microcontroller intends to do a READ operation.
A LOW level on this pin indicates that the microcontroller intends to do a WRITE
operation.
COMMAND/DATA selection from the host microcontroller.
92
C/D
When C/D=0, the data on the 8-bit data bus (DB0~DB7) are either code data to be
Input written to an internal register, or status from the internal Status Register.
93
94, 95
96
97
CL
CLK1, CLK2
E
FRM
Input
Inputs
Input
Input
When C/D=1, the data on the 8-bit data bus (DB0~DB7) are data to be written to or
read from the Display Data Memory.
COMMON scan clock supplied by the SBN6400G.
The time duration of a COMMON output is equal to one clock period of CL.
Two-phase clocks for the control logic.
These two clocks are generated by the timing circuit of the SBN6400G COMMON
Driver.
Enable signal (E) from the host microcontroller.
Frame signal from the SBN6400G, indicating the start of a new frame.
2005 May 20
9 of 37
data sheet (v3)