KSZ8462HLI-EVAL Datasheet, PDF (9/12 Pages) List of Unclassifed Manufacturers – KSZ8462HL Evaluation Board User Guide

KSZ8462_eval_bd_user_guide_1.0.docx
3.5 10/100 Ethernet PHY Ports
There are two 10/100 Ethernet PHY ports on the KSZ8462HL evaluation board. The ports can be
connected to an Ethernet traffic generator or analyzer via standard RJ-45 connectors using CAT-5 (or
better) UTP cables. Both ports support auto MDI/MDI-X, eliminating the need for cross-over cables.
Transformers are utilized for proper interfacing to an Ethernet network. In addition, optional over- voltage
protection devices D5 thru D12 may be installed to protect the KSZ8462 in the event of an over- voltage
condition.
For 10/100 Ethernet, the FXSD1 and FXSD2 pins should be pulled low by installing jumpers on pins 3 & 4
of J12 and J13.
3.6 100BASE-FX Fiber Port Option
There are two 100BASE-FX PHY ports on the KSZ8462HL evaluation board, which are not populated with
necessary components. The ports can be connected to an Ethernet traffic generator or analyzer via fiber
transceiver and fiber cable. In 100BASE-FX operation, both fiber signal detect input FXSD1 and FXSD2
are usually connected to the fiber transceiver SD (signal detect) output pin. This is done by jumpering pins
1 & 2 of J12 (Port 1) and J13 (Port 2). No jumpers are required on JP77 and JP78 except as noted below.
Capacitors C5 and C6 are also generally not required.
100BASE-FX is supported by the KSZ8462FHL. All KSZ8462 devices power up in copper mode. Fiber
Mode is selected by clearing the appropriate bits in the GFCR register (0x0D8 – 0x0D9).
The fiber signal detect threshold is set to 1.7V internally, When FXSD is less than the threshold, no fiber
signal is detected and a far-end fault (FEF) is generated. When FXSD is over the threshold, the fiber
signal is detected. To ensure proper operation, a resistive voltage divider is recommended to adjust the
fiber transceiver SD output voltage swing to match the FXSD pin’s input voltage threshold.
Alternatively, the user may choose not to implement the FEF feature. In this case, the FXSD input pin may
be pulled high via jumpers JP77 and JP78.
3.7 LED Indicators
The KSZ8462HL evaluation board provides two LEDs (PxLED1, PxLED0) for each PHY port. The LED
indicators are programmable to four different states. LED mode is selected through bits [9:8] of the
SGCR7 register (0x00E-0x00F).
The LED mode definitions are specified in Table 7. See Figure 2 for the LEDs’ orientation on the
KSZ8462HL evaluation board in the power supply section.
SGCR7 Control Register (0x00E-0x00F) Bits[9:8]
00 (default)
01
10
PxLED1 = Speed
PxLED1 = Active
PxLED1 = Duplex
PxLED0 = Link/Active PxLED0 = Link
PxLED0 = Link/Active
Table 5 LED Functions
11
PxLED1 = Duplex
PxLED0 = Link
Micrel, Inc.
Confidential
July 17, 2013
Rev. 1.0
9/12