KSZ8462HLI-EVAL Datasheet, PDF (7/12 Pages) List of Unclassifed Manufacturers – KSZ8462HL Evaluation Board User Guide

KSZ8462_eval_bd_user_guide_1.0.docx
The voltage level on all interface pins (VDD_IO) can be set to 1.8V, 2.5V or 3.3V of operation, enabling a
direct connection to different type of host processors.
Signal Pin No.
SD[15:0] 5-20
CMD 28
CSN 23
INTRN 31
RDN 36
WRN 35
PME/ 27
EEPROM
RSTN 24
+5V
GND
N.C.
1, 3
2, 4, 21,
22, 25,
26, 29,
33, 34,
37-40
30, 32
Type
I/O
Input
Input
Output
Input
Input
Output/
Input
Input
Function
Shared Data Bus
In 16-bit mode:
SD[15:0] -> D[15:0] data access when CMD = “0”.
SD[10:2] -> A[10:2] address access and SD[15:12] -> BE[3:0] byte enable
access when CMD = “1” (SD[1:0] and SD[11] are not used).
In 8-bit mode:
SD[7:0] -> D[7:0] data access when CMD = “0”.
SD[7:0] -> A[7:0] 1^st address access and SD[2:0] -> A[10:8] 2^nd address access
when CMD = “1” (SD[7:3] are not used during 2^nd address access).
Command Type
This command input determines the SD[15:0] shared data bus access cycle
information.
0: Data access
1: Command access for address and byte enable
Chip Select Enable
Chip Enable is an active low signal used to enable the shared data bus access.
Interrupt
This low active signal asserted low when an interrupt is being requested.
Asynchronous Read
This low active signal is asserted to low during a read cycle.
A 4.7K pull-up resistor is recommended on this signal.
Asynchronous Write
This low active signal is asserted low during a write cycle.
Power Management Event
This output signal indicates that a Wake On LAN event has been detected. The
KSZ8462HL is requesting the system to wake up from low power mode. Its
assertion polarity is programmable with the default polarity to be active low.
EEPROM select Configuration Mode
During Power-on/Reset time this pin is an input and the strap-in value is read
by KSZ8462HL to determine the presence of an EEPROM. (see description of
JP303 in Table 1)
Reset
This is the Hardware reset pin. It is active Low. This reset input is required to
be low for a minimum of 10 ms after supply voltages VDD_IO and 3.3V are
stable.
Power supply
Connection to +5V supply of the Host processor board.
Ground
Table 3 Signal Descriptions on the Parallel (Host-Port) Connector J16
Micrel, Inc.
Confidential
July 17, 2013
Rev. 1.0
7/12