UG-6028GDEBF02 Datasheet, PDF (8/28 Pages) List of Unclassifed Manufacturers – Product Specification

WiseChip Semiconductor Inc.
1.6 Block Diagram
Doc. No: SAS1-0I013-A
Active Area 1¹.^.4⁶5⁹"^”
160(RGB) x 128 Pixels
C1, C3, C5 : 0.1µF
C2 : 4.7µF
C4, C6 : 4.7µF / 25V Tantalum Capacitor
R1 : 68KΩ
R2 : 5.1KΩ
~
R1
C3
C4
~~~
SEPS525
~
R2
~
C1
C2
C5
C6
MCU Interface Selection
: Base on CPU、PS connection and Register setting (14h &16h).
Pins connected to MCU interface : D17~D9, RS, CSB, RDB, WRB, and RESETB.
Pins connected to RGB interface : D17~D12, VSYNC, HSYNC, DOTCLK, and ENABLE.
EIM=1(default)
Interface mode
4-wire SPI
80xx parallel 9 bit
80xx parallel 8 bit
68xx parallel 9 bit
68xx parallel 8 bit
PS CPU DFM1 DFM0 D17 D16 D15 D14 D13 D12 D11 D10 D9 RS CSB RDB WRB RESETB
0 X X X SCL SDI NC 0 0 0 0 0 0 RS CSB 0 0 RESETB
1 0 1 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 RS CSB RDB WRB RESETB
1 0 1 1 D7 D6 D5 D4 D3 D2 D1 D0 0 RS CSB RDB WRB RESETB
1 1 1 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 RS CSB E R/W RESETB
1 1 1 1 D7 D6 D5 D4 D3 D2 D1 D0 0 RS CSB E R/W RESETB
EIM=0
Interface mode
RIM1 RIM0 D17 D16 D15 D14 D13 D12 D11 D10 D9 VSYNC HSYNC DOTCLK ENABLE
6-bit RGB interface 1
0 D5 D4 D3 D2 D1 D0 0 0 0 VSYNC HSYNC DOTCLK ENABLE
Note:
1. DFM1、DFM0 setting by Register 16h
2. EIM、RIM1、RIM0 setting by Register 14h
3. “X” : Don’t care, “NC” : Non-connection
“1” : Connect to VDD or set to High level.
“0” : Connect to GND or set to Low Level.
http://www.wisechip.com.tw
4D Systems Pty Ltd
5
www.4dsystems.com.au